When there is no earnings call to read, no guidance to check against, and no post-call filing to reconcile, a publication drop is one of the few disclosure records that arrives on a fixed schedule regardless of what anyone wants to say that quarter. It is a thin instrument. It tells you what an assignee filed, roughly eighteen months to several years before the day it appears, and nothing about whether any of it works or ships. But the distribution of a drop is a fact, and on July 16, 2026, Huawei's distribution is the most legible thing about it. Fifty-two US applications published that day carrying a Huawei assignee. The count splits across three distinct assignee strings, which should not be merged: 49 to HUAWEI TECHNOLOGIES CO., LTD., two to Huawei Digital Power Technologies Co., Ltd., and one to Huawei Cloud Computing Technologies Co., Ltd. The subject matter is overwhelmingly what you would expect — wireless and 5G communications, antennas, handset interaction, foldable hinges, displays, health and wearables, and neural-network software. Exactly one of the 52 is a memory, SRAM, transistor, or semiconductor-device record.

The outlier

That record is US20260206566A1, "STATIC RANDOM-ACCESS MEMORY ARRAY, MEMORY, AND ELECTRONIC DEVICE," published July 16, 2026 with kind code A1 and classified under CPC H10W 20/2128, H10B 10/12, and H10W 20/435. It is a continuation of PCT/CN2024/097127, filed June 3, 2024, claiming priority to CN 202311183082.3, filed September 13, 2023. Six inventors are named: Weiliang Jing, Shihui Yin, Xiaoxuan Zhao, Ying Wu, Zhengbo Wang, and Heng Liao. The record establishes that those six are named inventors and nothing further about any of them — not a role, not a title, not a rationale. Inventorship is not strategy, and this document does not speak to either.

The problem the application takes up is a familiar one. A standard six-transistor SRAM bit cell places all six transistors side by side in the substrate, built with the front-end-of-line process, so the cell's area is the sum of six footprints. The BACKGROUND section explains why shrinking them is a dead end: the six have different performance requirements — per the record, the pull-down transistor carries the highest turn-on requirement, the access transistor next, the pull-up transistor the lowest — and transistor size drives turn-on performance. Shrink everything to buy density and you give back performance. The applicant's characterization of the prior art is blunt: the sizes "cannot be further reduced with miniaturization of a process node," and SRAM density improvement stalls there.

The proposed answer is to stop laying the cell out flat. Independent claim 1 recites a semiconductor substrate, a front-end-of-line device layer disposed in it, a back-end-of-line device layer disposed on the front-end-of-line layer, and a plurality of memory cells, each comprising at least one P-type and at least one N-type field-effect transistor — with the PFET formed in the FEOL layer and the NFET formed in the BEOL layer. Claim 2, a dependent claim, is what actually licenses the word "stacked": it recites that the NFET's orthographic projection on the substrate at least partially overlaps the PFET's. That is where vertical overlap of footprints is recited; claim 1 alone says only that the two transistors live in different layers. The record runs 20 claims. Per the SUMMARY, the role split is deliberate — the NFET becomes the pull-down transistor, the one with the highest turn-on requirement, and gets the back-end-of-line process; the PFET becomes the pull-up transistor, the lowest requirement, and stays in the front-end-of-line. The abstract offers the 6T and 8T cell as examples; the SUMMARY additionally mentions a 3T cell.

On the payoff, the SUMMARY says this:

Through use of the process structure, a vertical projection region of a memory cell can be reduced to 2/N of that of an existing structure (all transistors of a memory cell are made by using the front-end-of-line process). The memory density can be significantly improved.— STATIC RANDOM-ACCESS MEMORY ARRAY, MEMORY, AND ELECTRONIC DEVICE, US20260206566A1

That "2/N" is exactly as printed in the record, and N is not defined in the passage. It is reproduced here as the applicant wrote it. It is also worth being precise about what kind of statement it is: an applicant's assertion in a summary section, not a measured benchmark, not a third-party result, and not something the document supports with fabrication data — because the document contains none. This is a published application. Publication means the application was laid open, not that it was examined to allowance, and certainly not that anything described in it has been built, taped out, or yielded.

Reading the distribution, not more than the distribution

The temptation with a record like this is to reach for the surrounding drop and assemble a cluster. There isn't one. The other 51 applications from that day do not form a related-art cohort around the hero, and nothing in them touches transistor stacking or memory density. The nearest hardware-adjacent records are genuinely unrelated to it: US20260205142A1 is a forward-error-correction encoder framed as a chip; US20260206396A1 is a display drive backplane bonded to an epitaxial wafer, wafer-bonding work in service of microLED rather than logic; US20260202631A1 is optical-module packaging. US20260203175A1 uses the word "memory," but it means system RAM shared across datacenter hosts for virtual-machine failover — it is not a memory-device record and does not belong next to the hero. Those are the rest of the day's drop, listed to show what the day actually contained, not to suggest a throughline that the records do not have.

So the signal is the shape of the distribution itself: one silicon record in 52, arriving from a priority chain that starts in September 2023, in a drop otherwise given over to radios and handsets. That is a fact about a disclosure record, and it is the extent of what this document underwrites. The application does not name a foundry, a process node, a product line, or a schedule — it says "process node" generically and never names one. It makes no comparison to anyone else's approach and claims no priority over other back-end-of-line transistor work. Whether the structure it describes is manufacturable is not addressed anywhere in it. What Huawei has published is a description of an SRAM array that splits the bit cell across two device layers, presented as a route past the transistor-sizing limit that has capped SRAM density. That is the story, and it does not need to be a bigger one to be worth logging.