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Semiconductors
- TSMC's Aug. 20 Filings Cluster Around Backside Power and Packaging
- Intel's 40-Grant Day Reaches Down to Transistor-Scale Refrigeration
- Sixteen Applications in One Day, and Half of Them Are About the Seam Between Dies
- The second week running that the backside grants keep issuing
- A claim on what one bonder tells the next one
- The filing is about a bond. The exposure is about a second supply chain
- Micron Is Moving DRAM's Disturbance Bookkeeping Inside the Refresh Window
- IBM's Newest Chip Patent Runs the Backside Wiring Backwards
- ASML Application Describes a Die-Placement Machine Aimed at Heterogeneous Integration
- Huawei Published 52 Applications on July 16. Exactly One Was About Silicon.
- TSMC's July 16 Drop Keeps Circling the Underside of the Wafer
- A Glass-Core Packaging Cohort Comes Into View at Intel
- Intel's Pub Drop Reads Like a Leading-Edge Logic Roadmap, Not a Packaging One
- Belden Closes RUCKUS Acquisition, Funds It With a $1.85B Term Loan
- Lattice Lines Up $1.15B in Credit — a $200M Revolver and a $950M Delayed-Draw Term Loan to Fund the AMI Deal
- SiTime Closes ~$1.5B Renesas Timing Buy, Funds It From Cash and Adds an Undrawn Revolver
- Intel's June 30 Grant Cluster Signals a Concentrated Push Into Glass-Core Advanced Packaging
- Micron's Fiscal Q3 2026 8-K Reports $41.46 Billion in Revenue and $24.67 GAAP Diluted EPS
- onsemi to Absorb Synaptics in All-Stock Deal: The 1.350 Exchange Ratio and What the 8-K Sets Out
- TSMC's June 25 Filing Wave Concentrates on Backside Power and Wafer-Level Packaging
- Cerebras' First Earnings as a Public Company: Reading the Q1 2026 8-K Line by Line
- Two Quantum-Computing Firms Advance Nasdaq de-SPAC Listings in the Same Session
- Ambiq Micro Files S-1 to Sell 1.8M Shares at $90.48, Targeting ~$152M Net
- Semiconductor Purchase Commitments: The Off-Balance-Sheet Supply Bet in the Footnotes
- SEC Risk-Factor Disclosure (Item 105): How to Read a Chip Company's Stated Exposures
- Customer Concentration Disclosure: How Chip Makers Report Dependence on a Few Buyers
- Operating-Segment Reporting for Chip Companies: What the Segments Reveal and Hide
- Semiconductor Inventory Write-Downs: How Excess and Obsolete Charges Hit Chip Margins
- Foundry vs Fabless: How the Two Semiconductor Business Models Split Cost and Risk
- The Semiconductor Capex Cycle: How Chip Makers Disclose the Spending That Builds Capacity
- Semiconductor Gross Margin: How Chip COGS, Mix, and Inventory Charges Set the Number
- Intel's Newly Published Filings Cluster on Glass-Core Packaging and Through-Glass Vias
- Toshiba's Published Filings Point Toward Neuromorphic Compute and SiC Power Devices
- Intel's Week of Grants Mapped the Data-Center Memory and Chiplet Layer, Not the Core
- A NAND Maker's Published Filings Point Beyond NAND, Toward Oxide-Channel and Ferroelectric Memory
- TSMC's Week of Chip Grants Landed on Backside Power and Packaging, Not Logic Speed
- Intel's Published Filings Point to Forksheets and Backside Power
- TSMC's Nanosheet Grants: The Transistor IP Issued in One Cycle
- Samsung's DRAM Cell Filings Point Toward a New Channel Material
- What Micron Locked In: 27 Memory Patents Issued in a Single Week
- SK hynix Applications Point Toward Memory That Does Its Own Math
- Intel's April Grants Map a Push to Stack Memory Directly Into Logic Chips
- Micron's Latest Applications Put Compute Inside the Memory Array — A Read on Where the R&D Is Going
- China's Leading DRAM Maker Logged 29 U.S. Memory Patents in One Week — Here's What They Cover
- TSMC's Published Filings Put the Cooling Inside the Package
- Intel Is Patenting Memory Stacked on Logic — and the Cooling to Keep It Cold
- Micron's Published Filings Point at Faster, Denser NAND
- NVIDIA's Week of Grants Reaches Past the GPU, Into the Rack
- Applied Materials' Newly Published Filings Point at the Boring Steps That Gate 3D Scaling
- Qualcomm Is Patenting the Inside of the Chip, Not Just the Modem
- SK hynix's Newly Published Filings Split Between Stacking Chips and Stacking Memory Cells
- IBM Led the Week's Chip Grants — and It Spent Them on Power and Stacking, Not Logic Speed
- onsemi's New Filings Point at Solderless, Higher-Reliability Power Modules
- Intel's May 26 Grants Map a Package Built From Stacked Dies
- Samsung's Newly Published Packages Put Optics Next to the Processor
- TSMC's Packaging Grants Pile Up: What the June 2 Issue Locked In
- TSMC's June Patent Drop Splits Two Ways — and Both Point at the Same 2nm Bet
- Intel Is Building Its Foundry Comeback in the Package, Not the Transistor
- USTR Pulls the Section 301 Trigger on Brazil: A Tariff Action With an Electronics-Cost Tail
- How Export Controls Get Loosened, One Country at a Time: DOE Adds Thailand to Its Generally Authorized List
- Commerce Keeps the Subsidy Finding on Chinese Solar Silicon: Reading the 2023 Countervailing-Duty Preliminary Results
- The Pentagon's Latest 'Chinese Military Company' Designation List — and Why Chip Buyers Treat It as a Procurement Tripwire
- Washington Implements the Taiwan MOU: What the Section 232 Tariff Changes Signal for the Chip Supply Base
- A New Section 337 Memory-Chip Case: MonolithIC 3D's Five-Patent Complaint and the Import Risk It Creates
- The Government Is About to Tell Every Contractor Which Chips It Can't Buy
- The CHIPS Industrial Advisory Committee Is Where the R&D Money Gets Graded
- USTR Opens a Sweeping Section 301 Probe Into Manufacturing Overcapacity — Chips Are in the Crosshairs
- A New Countervailing Duty Order on Laotian Silicon Metal Closes a Supply-Chain Backdoor
- Commerce Finds China Still Subsidized Solar Cells in 2023 — A Preview of How It Polices the Whole Silicon Supply Chain
- The Taiwan Tariff MOU Is Now Law in the Tariff Schedule — and Chips Are the Subtext
- TSMC's Liquid-Cooled-Lid Patent: Thermal Is the New Scaling Limit
- TSMC's Backside-Power Patent: What the Foundry Is Actually Buying Itself
- The AI Capex Supercycle, Read From Five Filings Instead of Five Headlines
- Intel's Stacked-Memory Package Patent and Why Packaging Is the Real AI Bottleneck
- Intel's Gate-All-Around Grant Is a Manufacturing Bet, Not a Marketing One
- Memory Bandwidth Through Vertical Connections: Reading AMD's Xilinx Grant
- The Overlooked AI Capex: A Liquid-Cooling Patent and the Datacenter Build
- TSMC's Pattern-Formation Patent and the Lithography Margin Lever
- Applied Materials' EUV Vacuum-Bake Patent and the Equipment Layer's Quiet Leverage
- TSMC's Nanosheet Gate-Patterning Patent Is Really a Yield Story
- The Other Chip Market: Mitsubishi's Power-Semiconductor Patent and Where the Volume Is
- NVIDIA By the Numbers: Revenue That Tripled, Then Doubled Again — From the Filed Tables
- IBM's Stacked-Transistor Patent and the Next Lever After Gate-All-Around
- Intel's Photonic-Die Patent and the Bet on Light Between Chips
- TSMC Tells You Where the Growth Came From: 3nm and 5nm, in the 20-F
- Intel Foundry Is Now Its Own Reportable Segment — Why That Disclosure Is the Story
- TSMC's Own Words on Fab-Expansion Risk: The 20-F Behind the Capex Supercycle
- Micron's HBM-to-DRAM Swing Risk: The 10-Q Sentence That Prices the Memory Cycle
- ASML's EUV, As the 20-F Defines It: 13.5 Nanometers and the Whole Leading Edge
- NVIDIA's Networking Just Grew 142% — Reading the FY26 10-K Line, Not the Headline
- AMD's Instinct Roadmap, As the 10-K Names It: MI200, MI300, MI325, MI350
- Micron's HBM Franchise Crossed $10B — Up More Than Fivefold, From the Proxy
- What NVIDIA's China Data-Center Disclosure Actually Says — Word for Word
- Broadcom's Custom-Silicon Story: Where to Actually Read It in the FY25 10-K
- Tokyo Electron's 2025 Vertical-DRAM Patent: When the Equipment Maker Owns the Recipe
- Intel's 2025 3D NAND Air-Gap Patent: Fighting Interference With Empty Space
- NVIDIA Releases $180 Million of H20 Reserves - But Reports No H20 Sales to China
- IBM's 2025 Scaled 2T-DRAM Patent: Rethinking the Memory Cell Itself
- TSMC's 2025 Underfill-Crack Patent: Reliability as a Quiet Cost Center in Packaging
- NVIDIA Takes a $1.9 Billion H20 Inventory Charge - The Q1 FY26 10-Q Quantifies the China Hit
- Samsung's 2025 Fan-Out Package Patent: When the Package Becomes the Product
- Samsung's 2025 Vertical-DRAM Patent and the Next Density Frontier After 3D NAND
- Winbond's 2025 3D NAND Patent and the Cost-per-Bit Race That Defines Flash
- Samsung's 2025 3D Flash Patent: Shaving Wire Length to Win the Efficiency Grind
- Dialog's 2025 Embedded-Inductor Package Patent: Pulling Power Components Into the Package
- Broadcom's 2024 Copper-Bonded Memory-Stack Patent and the Custom-Silicon Edge
- Mitsubishi's 2024 SiC Power-Conversion Patent as an Electrification Demand Marker
- Micron's FY2024 10-K Puts HBM in the Core Portfolio - The AI-Memory Lane Is Now Named
- One Customer Is a Significant Slice of NVIDIA's Data Center Revenue - The Q2 FY25 10-Q Flags It
- TSMC's 2024 Thermal-Package Patent: When Getting Heat Out Becomes a Capex Decision
- Eliyan's 2024 Network-Attached Memory Patent and the Die-to-Die Interconnect Startup Bet
- Mitsubishi's 2024 SiC-and-Converter Patent: Capturing Value at the System Level
- Ayar Labs' 2024 In-Package Optical I/O Patent: When Optics Reaches the Memory Wall
- Intel's 2024 EMIB-and-Interposer Patent: The Bridge Strategy Behind Its Packaging Pitch
- TSMC's 2024 Memory Thermal-Throttling Patent: When Slowing Down Is the Feature
- Mitsubishi's 2024 SiC Patent and the Power Incumbent That Keeps Filing
- Infineon's 2024 SiC Trench Patent and Europe's Position in the Power-Chip Supply Chain
- Broadcom's FY2023 10-K Records the VMware Close - The Software Pivot Is Now on the Balance Sheet
- IBM's 2023 Nanosheet Threshold-Voltage Patent: The Tuning Lever Inside the 2nm Transistor
- IBM's 2023 Wrap-Around-Contact Patent and the Resistance Problem at the Leading Node
- IBM's 2023 Gate-All-Around Isolation Patent: A Density Step Behind the 2nm Story
- Marvell's 2023 Co-Packaged Optics Patent and the Bandwidth Wall in the Network Switch
- TSMC's 2023 EUV Pellicle Patent and the Hidden Yield Tax on Leading-Edge Lithography
- Samsung's 2023 EUV Mask-Inspection Patent and the Defect Economics of Leading-Edge Nodes
- TSMC's 2023 GAA-and-Planar Patent: The Hidden Cost of a Transistor Transition
- Intel's 10-K Commits to Five Nodes in Four Years - and an Internal Foundry Model
- Qualcomm's 2022 Stacked-Die Voltage-Regulator Patent: Pulling Power Into the Package
- Sungrow's 2022 IGBT-Module Patent and the Inverter Supply Chain Behind Renewables
- NVIDIA's A100 and H100 Now Face China Export Limits - The 10-Q Says So
- AMD's Q3 2022 10-Q Now Carries Xilinx and Versal - The Integration Shows in the Filing
- Qualcomm's 2022 3D Backside-Power Patent: When Mobile Silicon Met 3D Integration
- TSMC's 2022 Backside Power-Rail Patent: A Node Feature Hiding in a Process Method
- TSMC's 2022 Hybrid-Bonding Patent and the Packaging Step That Walls Off Competitors
- A 2022 Double-Gate IGBT Patent and the Switching-Loss Lever in Power Conversion
- Xilinx's Stacked Power-Delivery Patent and the AMD Acquisition Thesis Written in IP
- imec's 2021 Backside-Power Patent: The Research Edge That Foundries Later Industrialized
- A 2021 GaN Breakdown-Voltage Patent and the Reliability Gate on Power Electronics
- Reading Micron's FY2021 10-K: DRAM, NAND, and the Two Engines of a Memory Cycle
- Micron's Q3 FY21 10-Q: Where Managed NAND Quietly Reshapes the Cost Stack
- Qualcomm's 2021 GaN Transistor Patent and the RF-Power Position Behind the Modem Business
- Apple's 2021 Fanout-Interposer Chiplet Patent: When Packaging Became the Strategy
- NVIDIA's RTX 30 Launch, As the Q3 FY21 10-Q Tells It
- Fuji Electric's 2020 SiC Grant and Japan's Quiet Hold on the Power-Chip Supply Chain
- The SiC MOSFET Patent That Marks Where the Other Chip Market Was Going in 2020
- Rambus's 2020 Stacked-DRAM Patent: The Memory-Bandwidth Bet Placed Before the AI Boom
- Apple's 2020 Tiered-Memory Patent and the Bandwidth-vs-Capacity Tradeoff in One Document
- Fuji Electric's 2020 SiC Epitaxy Patent: Why Yield, Not the Device, Is the Power-Chip Business
- NVIDIA's FY2020 10-K Names Four Markets - And the Data Center Bet Hiding in Plain Sight