Sixteen patent applications assigned to Intel Corporation published on August 6, 2026 — fifteen under the assignee string “Intel Corporation” and one under “INTEL CORPORATION,” a casing split that has to be summed rather than read off a single facet. Sorted by subject matter, the set is lopsided in a way that is worth recording.

Six of the sixteen are directed to package construction: bridge dies and redistribution layers, chiplets sharing a metallization stack, solder-joint defect control, stacked memory vias, and coolant flow through an immersion tank. Two more are directed at the protocol running across a die-to-die link. Three concern the arithmetic and data movement inside an AI accelerator. Three are wireless signalling, and two — a video quantisation-parameter technique and a trusted-execution-environment protection — sit outside any cluster. Eight of sixteen, then, are about the seam between pieces of silicon.

The lead record is US20260231831A1, and what distinguishes it is not the bridge — bridges are well-trodden ground — but how specifically its claims describe what is being bridged. The independent claim recites a first high bandwidth memory, a first graphics processor unit die, a second GPU die and a second HBM, each over a named position in a three-die lower tier. Packaging claims are usually drafted in the abstract, in first-die and second-die language, precisely so that they are not confined to one product configuration. This one names the payload by function.

conductive pillars in the second insulating material, the conductive pillars laterally spaced apart from the first die, the second die and the third die, the conductive pillars having a same vertical thickness as a vertical thickness of the second insulating material— HIGH PERFORMANCE MICROELECTRONIC ASSEMBLIES INCLUDING THROUGH-SILICON VIA BRIDGES WITH TOP DIE FIRST APPROACH, US20260231831A1

The quoted element is the routing mechanism. The pillars stand beside the bridge dies and run the full height of the insulating material, so the upper redistribution layer reaches the lower one without passing through silicon. In commercial terms that is the part that determines how much of a large package's power and lower-speed routing has to be designed around the bridge tier. It is disclosed alongside a supporting detail — the three lower dies are each thinner than the insulator around them — that makes the pillars, not the dies, the thing setting the tier height.

The clusters, and what they do not say

The packaging group runs in two directions at once. One application describes a disaggregated package in which IC dies sit directly on a bridge die with no redistribution layer in that path — fewer layers, tighter coupling. The lead record adds two redistribution layers and pillars to span them. Both are on the record on the same day, which is what a portfolio covering a design space looks like rather than a commitment to one answer. A third addresses head-and-pillow open defects during thermal compression bonding, a yield problem that scales with die count and warpage; a fourth runs shared metallization across adjacent chiplets on a common base layer.

The interconnect pair — a die-to-die adapter that selects a data format from link parameters, and clock-phase management that holds a roughly 90-degree offset between clock and data at the receiver — sits at the same seam from the logic side. The AI group covers four-bit floating-point processing via scaled five-bit integers, on-chip decompression and sparsity decode, and reinforcement learning split across heterogeneous processors with weights moved over point-to-point channels. Between them the day's filings describe a stack from the solder joint to the number format, with immersion cooling handling what the stack gives off.

Reading the timing honestly

Two limits belong on any inference drawn from this. First, these are published applications, not granted patents. Nothing here has been examined to allowance, and claim scope at publication is what the applicant asked for, not what it will receive. Second, US applications publish roughly eighteen months after their earliest priority date, so a publication set dated August 2026 reflects choices made well before it. It is evidence about the direction of work, not about the current quarter.

With those caveats, the distribution still says something. A packaging portfolio that names GPU dies and HBM stacks in its independent claims is drafted against a specific class of product, and the surrounding filings — the D2D adapter, the clock phase control, the immersion cooling, the low-precision arithmetic — describe the rest of that product. The set coheres. That is a different signal from sixteen unrelated applications happening to share a publication date.

One structural point in the lead record deserves separate mention because it bears on supply chain rather than design. The claims require that the outer two dies of the lower tier carry through-silicon vias and that the middle die does not. TSV-bearing dies and non-TSV dies are different manufacturing flows with different cost and yield profiles, and a claim that fixes which positions get which is a claim about how the tier is sourced and assembled, not only about how it is wired. The same asymmetry recurs across the claim 8 and claim 14 families, so it is not an artefact of one embodiment.

What the record does not disclose is equally worth stating. None of these applications names a product, a process node, a customer or a manufacturing site. None discloses volumes, yields or licensing. The floorplan in the lead record's claims is a described embodiment, and a claim that recites GPU dies is a claim about the shape of an assembly, not an announcement that such an assembly is being built. Readers wanting the underlying scope should go to the claim set itself rather than the abstract, whose 3,000-to-9,000-square-millimetre area range appears in none of the twenty claims.