Taiwan Semiconductor Manufacturing (TSM) was issued roughly 60 US semiconductor patents in the week ending March 27, 2026, placing it among the highest-volume assignees of the week alongside International Business Machines and Samsung Electronics. For the world's largest contract chipmaker, the count itself is unremarkable; what is informative is where the grants landed. Read as a set, the week's issued patents concentrate not on logic-transistor speed but on the layers that surround the transistor — how power reaches stacked devices, how dies are packaged together, and how memory is assisted on-chip. Those are the layers that have become the gating constraint on AI-accelerator integration, and a granted claim is enforceable coverage on the methods involved.

That distinction matters for how a foundry competes. TSMC sells manufacturing and the process IP that surrounds it; its patent estate is the connective tissue customers design into. A week of grants weighted toward power delivery, packaging, and embedded memory is coverage staked across the integration layers every advanced-node customer has to traverse, rather than a bet on a single device feature.

Backside power for stacked transistors

The first theme is power and signal routing for stacked transistors — building one device atop another and moving the power rails to the back of the wafer to free front-side routing. TSMC was granted US12588492B2 and the companion US12588491B2, both covering front-side and back-side power-rail and signal-line arrangements in integrated circuits having stacked transistors, plus US12588488B2, which covers a back-side conductive-line structure connected to a gate through a feed-through via. The complementary-FET idea — stacking an n-type device over a p-type device — is one of the structural moves the whole industry is converging on for sub-2nm density, and the power-rail routing is what makes the stack usable. One of the stacked-transistor grants states the arrangement plainly:

The front-side power rail is conductively connected to a second source conductive segment intersecting the second-type active-region semiconductor structure.— Power rail and signal line arrangement in integrated circuits having stacked transistors, US12588492B2

Coverage on how front-side and back-side rails connect to stacked devices sits underneath any customer design that adopts the stacked-transistor approach the foundry's roadmap points toward. That is the kind of position a manufacturer accumulates to protect the process it sells, distinct from a fabless designer protecting a product architecture.

Packaging is the second center of gravity

The denser theme by raw count is advanced packaging — the discipline that has displaced raw wafer fabrication as the AI bottleneck. US12588554B2 covers an integrated-circuit package substrate with a heterogeneous bonding scheme combining conductive pillars and embedded connectors to bond multiple dies. US12588549B2 covers an interposer-wafer package using a stiffener structure attached alongside the die. US12588525B2 covers a packaging substrate with an underfill-injection opening for a die-and-interposer assembly, and US12588523B2 covers fan-out package-on-package structures with through-vias that have cavities. Heterogeneous bonding, interposers, stiffeners, and underfill are the mechanical and electrical plumbing of multi-die packages — the CoWoS-and-fan-out family that AI accelerators are built in. Issuing several package-construction patents in one week is coverage on the assembly steps, not the transistor.

The week's packaging grants also extend into the redistribution and thermal layers that surround the die. US12588482B2 covers a method for forming semiconductor redistribution structures with stacked bond vias and pads, and US12588505B2 covers a heat-sink structure with an embedded thermoelectric cooler positioned above two die interfaces. Routing and heat removal are the constraints that grow as more dies are packed into one package, and patenting them alongside the bonding and interposer work fills out a coverage map of the whole package rather than one feature of it.

Memory assist and compute-in-memory

The third theme moves on-chip, into the memory circuitry that feeds logic. US12586635B2 covers a static random-access memory write-assist circuit using two capacitive elements to couple a bit line to progressively lower negative voltages during a write. US12586628B2 covers adjusting word-line pulse width based on the physical distance of the addressed line from the controller. And US12587175B2 covers a reduced-power compute-in-memory system that suppresses latching when input data bits are all zero. Write-assist, pulse-width tuning, and compute-in-memory are the techniques that govern how fast and how efficiently embedded memory operates — increasingly the limiter on accelerator throughput, where moving data, not arithmetic, dominates the energy budget.

For a business reader, the through-line is what kind of company files this way. A fabless designer racing to a product would weight its grants toward a differentiating architecture. A foundry weights its estate toward the manufacturing and integration steps every customer has to pass through — power delivery, packaging, and the embedded-memory circuitry that customers rely on the process to provide. TSMC's week is the second pattern: backside power for stacked transistors, multi-die package construction, and on-chip memory assist, filed together rather than scattered.

The standing caution applies and cuts the way it always does: a granted claim is coverage, not revenue, and it says nothing on its own about adoption or licensing. What the week documents is position. By comparison, the same week's grants from IBM skewed toward emerging memory cells and device architecture — research a licensor stakes — while TSMC's skewed toward the power-rail, packaging, and memory-assist steps a manufacturer performs. That difference is the map: TSMC's March 27 grants put enforceable markers under the system-integration layers where AI-era chips are actually assembled.