The chokepoint fact first: the hardest-to-replicate capability in advanced computing is no longer the transistor — it is the assembly, and hybrid bonding sits at its center. US11322481B2, granted May 2022 to TSMC, patents hybrid bonding technology for stacking integrated circuits (CPC H01L 25/0657).
Gloss it once. Hybrid bonding connects two dies by directly fusing their copper pads and surrounding dielectric, with no solder bumps in between. That allows connections at far finer pitch — vastly more, vastly shorter links between dies than bump-based methods. It is the structural basis for the densest 3D stacks.
Why a chokepoint read cares: hybrid bonding requires extreme cleanliness, alignment, and process control, which means capacity is scarce and concentrated. When a leading foundry holds both the IP and the lines, downstream customers inherit a dependency that prices into the whole AI-hardware supply chain.
The period framing matters. In 2022, hybrid bonding was scaling from specialty applications toward mainstream advanced packaging. A TSMC grant at that moment marks the foundry consolidating IP at exactly the assembly layer that would become the visible bottleneck.
The caveat we attach: this is a process-and-structure patent and a defensive asset. It evidences TSMC's position in hybrid bonding; it does not by itself quantify capacity or prove a given product depends on it.
For the period investor, the durable point is that the moat moved into assembly. A 2022 hybrid-bonding grant from the dominant foundry is a marker of where the next chokepoint was being built — in the packaging, not the silicon.