The capex-meets-IP fact first: flash memory is the most commoditized chip there is, and it competes almost entirely on cost per bit — which is a manufacturing problem. US12250816B2, granted March 2025 to Winbond, patents a 3D NAND flash memory and its manufacturing method (CPC H10B 43/27).
Gloss it once. 3D NAND stacks memory cells vertically in many layers instead of spreading them across a flat die. More layers means more bits per wafer and lower cost per bit — but each added layer makes the manufacturing harder, with deeper etches and tighter tolerances. The whole industry races to add layers while keeping yield acceptable.
Why a capex desk reads it: in NAND, the manufacturing method is the business. A process patent that helps build the stack more reliably is a direct lever on cost per bit, which is the only metric that durably matters in a commodity memory. The capital goes into the fab and the process, and the IP protects the process edge.
The period framing matters. By 2025, layer counts in 3D NAND were extremely high and the engineering challenge was severe. A 2025 NAND-and-method grant reflects the continued grind of the cost-per-bit race, where the winner is whoever manufactures the tallest stack at yield.
The caveat we attach: this is a device-and-method patent and a defensive asset. It evidences process focus; it does not disclose layer count, yield, or cost.
For the period investor, the lesson is that NAND is a process-and-capex business with no escape into differentiation. A 2025 3D NAND grant is one move in a race measured purely in cost per bit.