SK hynix sits at the most strategically sensitive spot in the AI supply chain: it is the leading supplier of high-bandwidth memory (HBM), the stacked DRAM that AI accelerators cannot ship without, and it is a South Korean firm navigating U.S. export rules that govern which advanced memory can be sold where. So when its newly published patent applications start describing memory that does arithmetic rather than just holding it, that is a direction worth reading. A published application is a roughly 18-month-delayed snapshot of where R&D money went, and the SK hynix applications published on 16 April 2026 point past storage and toward compute.

The standout is US20260104859A1, which describes a processing unit, a processing-in-memory device, and a processing-in-memory system that performs arithmetic using a redundant residue number system (RRNS) — a non-binary way of representing numbers that splits a value across several moduli so operations can run in parallel and tolerate certain errors. The application is explicit that this is a processing-in-memory design, not a conventional logic block:

A processing unit includes a redundant residue number generation circuit configured to convert first operand data and second operand data into a plurality of first operand redundant residue number sets, and a plurality of second operand redundant residue number sets based on a redundant residue number system (RRNS) using first to T-th moduli.— Processing Unit, Processing-In-Memory Device, and Processing-In-Memory System Based on Redundant Residue Number System, US20260104859A1

The commercial logic behind it is the same memory-wall economics driving the rest of the sector: in AI workloads, the cost and power of moving data between the processor and memory often dominate the cost of the math itself. Processing-in-memory tries to perform some of that math inside the memory device, so the data moves less. For SK hynix specifically, this is adjacent to the franchise it already leads — HBM is valuable precisely because it shortens the distance between compute and memory, and a processing-in-memory capability would push that logic one step further, into the memory die. An application choosing an error-tolerant, parallel number system as the arithmetic base is a tell about designing for the kind of dense, fault-prone in-array computation that conventional binary logic handles awkwardly.

There is a geopolitical layer to reading SK hynix filings that does not apply as cleanly to a U.S. memory maker. As a Korean supplier of the HBM that AI accelerators depend on, SK hynix operates inside the same export-control framework that governs which advanced memory and which AI parts can ship to which destinations — the rules that have repeatedly reshaped the addressable market for high-end memory. A patent application does not disclose anything about where products can be sold, and nothing in this set speaks to compliance. But the direction the filings point — memory that carries more compute value, built on denser stacked NAND and HBM-style assembly — is the same capability that sits closest to the controlled frontier, which is part of why where a leading memory supplier is steering R&D is a business fact and not just a technical one.

The supporting filings: device and package

The rest of the published set covers the device and packaging layers a compute-capable memory roadmap needs. US20260107466A1 describes a 3D NAND device with a channel layer whose metal-atom concentration changes between an upper and a lower portion — channel engineering for the vertical stacking that keeps NAND scaling as planar density runs out. US20260107838A1 describes a semiconductor package with "dam patterns" that control how molding compound flows around the chips — the kind of assembly-yield work that matters acutely for stacked memory, where a packaging defect can scrap an expensive multi-die part. And US20260104747A1 describes a computing system that adjusts the memory power voltage via a power-management IC on the memory module based on the processor's voltage — power-delivery coordination between processor and memory, which becomes more delicate as memory takes on compute and the two sit closer together. A separate filing, US20260106452A1, covers a stacked-transistor electrostatic-discharge protection circuit — the unglamorous reliability layer that every shippable memory part needs. Read alongside the processing-in-memory unit, these supporting filings sketch the same end-to-end posture: a compute-capable memory is only useful if the underlying NAND stack keeps scaling, the package yields when several dies are assembled together, the power delivered to the memory tracks the processor it sits beside, and the device survives the electrical stresses of the field. SK hynix filing across all of those layers in one publication week is the footprint of a company treating compute-in-memory as a system problem rather than a circuit demo.

The caveats are the standard ones for applications, and they bite. These are publications, not grants: the claims can be narrowed or rejected before any patent issues, and a filed concept is not a shipping product. The 18-month lag means the set reflects R&D decisions made well before the publication date, not SK hynix's current roadmap. Processing-in-memory in particular has been a research theme across the memory industry for years without displacing conventional accelerators in volume, so the presence of this IP does not establish a product line. What the cluster establishes is direction and intensity: the leading HBM supplier is funding R&D not only on denser NAND and better packaging but on the harder, further-out problem of computing inside the memory — the part of the stack a memory maker would invest in if it intends to capture more of the value of AI systems rather than supply the storage layer beneath them. The same week's broader publications show memory and logic peers filing on adjacent in-array and device structures, which is what one expects when several large players are reading the same trend at once.