On May 26, 2026, Intel (INTC) was issued a cluster of patents that, read together, describe the assembly of a package built from multiple stacked dies rather than one monolithic chip. For a business reader, this is the layer where Intel's IDM 2.0 and foundry ambitions meet physics: as single-chip scaling slows, the value moves into how separately fabricated dies — chiplets — are stacked, bonded and wired into a working module. The grant cycle's records sit across several of those steps at once.

The plain-language version of the shift helps here. For decades, more performance came mainly from shrinking transistors on a single large chip. As that path slows and large chips grow expensive to make at high yield, designers increasingly split a product into smaller dies — chiplets — each potentially on a different process, then reassemble them into one package. The hard problems migrate to the seams: how to stack the dies, how to bond them with enough connections, how to route signals between them with low loss, and how to deliver power and remove heat. The May 26 grant cluster reads as coverage spread across precisely those seams.

The anchor record is US12642071B2, "Scalable architecture for multi-die semiconductor packages." It describes a first die with multiple cores stacked over a second die carrying DRAM, with through-silicon vias coupling each core directly to a local portion of memory. Placing memory directly beneath compute, connected by short vertical vias, is the structural answer to the bandwidth problem that defines AI and high-performance workloads.

The DRAM of the second die may have a plurality of local portions, each of the plurality of local portions associated with a second plurality of TSVs, where each of at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by the corresponding first and second plurality of TSVs.— Scalable architecture for multi-die semiconductor packages, US12642071B2

The bonding and substrate layers

The same grant date carried records covering how those dies are joined. US12642130B2 describes hybrid bonding a die — framed as a chiplet — to a substrate, with vias connecting metal pads on both sides of the die, and extends to multiple dies bonded to a substrate and to each other. US12642132B2 describes a die-stacking architecture for high-speed input/output in which through-dielectric vias are deliberately inclined "at an angle not equal to ninety degrees" — a geometric approach to routing between stacked dies. Both records describe interconnect mechanics rather than device physics: the question of how to get signals between dies that are no longer on the same piece of silicon.

The substrate itself appears in the cluster. US12642120B2, "Ultra low loss and high-density routing between cores," describes a package core built from stacked glass layers with traces between them — glass-core substrates being a materials shift aimed at finer routing and lower signal loss than organic substrates. A related memory-integration grant, US12642128B2 (assigned to Intel NDTM US LLC), describes a 3D NAND component with control circuitry split across two bonded wafers, freeing array area — another instance of the same wafer-bonding logic applied to memory. The cluster does not stop at packaging; the same grant date carried records at the transistor and interconnect level, which shows the coverage spanning the full stack. US12642069B2 describes transistor cells with a deep via lined with dielectric material, connecting a transistor terminal to interconnect on the opposite side of the substrate — a structure tied to backside power delivery, where power is routed from beneath the transistors rather than through the signal wiring above them. US12641850B2 describes a lattice stack for internal-spacer fabrication in gate-all-around devices with a stacked-transistor configuration, and US12642079B2 describes an interconnect feature recessed below the dielectric surface. Read alongside the packaging records, the grant cycle covers both how Intel builds the transistors and how it assembles the dies that contain them.

For a business reader the significance is in where these structures land in the product stack. Backside power delivery and gate-all-around transistors are the two architectural shifts most associated with leading-edge nodes; multi-die stacking, hybrid bonding and glass cores are the packaging shifts most associated with chiplet-based products. Having issued claims across both in one cycle is a fact about the breadth of the portfolio, not a claim about node leadership — the records describe structures, not shipping volume or yield, which are the things that actually determine competitive outcomes and which patents do not disclose.

Where the coverage sits relative to the cycle

The May 26 grant cycle included comparable packaging activity from other assignees, which a reader can weigh as fact rather than judgment. Samsung Electronics was issued US12642139B2 and US12642098B2, the latter covering a stacked-chip package with non-conductive bonding layers. Google LLC was issued US12642137B2 on a multi-layer chip architecture referencing qubit control elements. By the grant cycle's assignee facets, Samsung, Taiwan Semiconductor Manufacturing and Qualcomm each led the named semiconductor grants by raw count, with Intel's cluster concentrated specifically in the packaging and die-stacking subset.

What the records map is issued, enforceable coverage spanning the full assembly path of a chiplet package — stacking cores over local memory, hybrid-bonding dies to substrates, routing through angled vias, and building glass-core substrates. The grants describe the steps and structures, not a verdict on how the chiplet competition resolves. They show what one assignee locked in across that path on a single grant date, in the layers that have become the active front of semiconductor design as transistor scaling alone stops delivering the gains.