The capex-meets-IP fact first: marquee node features are sold as architecture but built as process, and the process is where the money goes. US11411100B2, granted August 2022 to TSMC, is a method of forming backside power rails (CPC H01L 29/66795) — the manufacturing side of a feature the industry markets heavily.
Gloss it once. Backside power delivery routes power rails under the transistors, freeing the front of the wafer for signal wiring. Actually forming those rails means thinning the wafer and building dense metal on the back, then connecting it to the devices — a sequence of new, expensive process steps. The method patent is about how to do that manufacturably.
Why a capex desk reads it: the difference between announcing backside power and shipping it profitably is yield on these backside steps. Process patents are where a foundry protects the operational know-how that turns a feature into a product. For TSMC, that protection is part of the moat its capital buys.
The period framing matters. In 2022, backside power was moving from research validation toward production planning at the leading foundries. A TSMC method patent at that moment marks the industrialization phase — the company committing engineering and, later, capital to making the feature real.
The caveat we attach: a method patent is a defensive asset and evidence of process investment, not a yield number or a capacity figure. It tells you TSMC was building the manufacturing IP; it does not disclose the economics.
For the period investor, the lesson is to read node features through their process patents. The architecture is the headline; the method grant is the confession of where the capital and the yield risk actually live.