The capex-meets-IP fact first: the 2nm story is sold as a transistor architecture but built from dozens of fine-grained process techniques. US11728340B2, granted August 2023 to IBM, patents single-diffusion-break isolation for gate-all-around (GAA) transistors (CPC H01L 27/0886).

Gloss it once. GAA transistors wrap the gate fully around the channel for better control at small sizes. “Single diffusion break” isolation separates adjacent transistors using a narrower break than older two-break schemes — which saves area. In a node where every square nanometer counts, isolation efficiency is a direct density lever.

“Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices.”— U.S. Patent No. 11,728,340 source

The patent’s mechanism is a reused dummy gate, and that reuse is where the area savings come from. Between two GAA transistors, the abstract and claim 1 place a single-diffusion-break isolation structure built as a “dummy gate structure” — a non-functional gate sitting on the substrate between the source/drain of the first device and the source/drain of the second. Rather than cutting a wide trench between cells, the design occupies one gate’s worth of pitch with an insulating dummy that electrically isolates the two source/drain layers (claim 4 states the structure “is configured to electrically isolate the first and second source/drain layers”). Because the break is the width of a single gate that the layout already budgets for, you reclaim the area an old double-break would have consumed.

The fabrication detail is what makes it a manufacturable density win rather than a wish. Claim 3 specifies that the stack of oxide layers in the break comes from “oxidized epitaxial silicon channel layers of a nanosheet stack structure” — in other words, the same nanosheet channels grown everywhere else are simply oxidized in the break region to form the isolation, so the isolation is built from the device’s own process steps. The claims also pin the materials: insulating fill from silicon nitride, silicon oxynitride, SiCOH, SiCH, or SiCNH (claim 7), embedded sidewall spacers from SiN, SiBCN, SiCO, or SiCON (claim 13), and gate electrodes of tungsten, ruthenium, cobalt, copper, or aluminum (claim 14). The work-function metal embedding the active channels (claim 1) is called out as compositionally distinct from the gate electrode metal — the kind of integration constraint that determines whether a single-break scheme actually yields.

Why a capex desk reads it: nodes get cheaper per transistor only if density improves, and density comes from exactly these incremental process techniques, not from the architecture alone. A single-diffusion-break scheme that reuses the nanosheet stack’s own oxidized channels to form isolation is a textbook example of squeezing area out without adding exotic steps. IBM is a research-and-IP powerhouse in logic process, and its grants map where the enabling techniques are being invented — often ahead of the foundries that license or independently develop them.

The period framing matters. In 2023, GAA was entering production at the leading foundries. IBM patenting GAA single-diffusion-break isolation at that moment — down to the oxidized-channel construction and the specific spacer and electrode materials — reflects the deep, distributed IP base underneath the 2nm transition: the techniques that make the marketing node real.

The material specificity in the claims is itself the signal worth reading. A single-diffusion-break scheme only works if the insulating fill, the embedded sidewall spacers, and the gate electrode metals are chosen so they isolate cleanly, etch predictably, and do not react with one another through hundreds of subsequent steps. The patent therefore enumerates options at each layer — nitrides and carbon-doped insulators for the fill, a related but distinct family for the spacers (claims 9–13 even cover the cases where fill and spacer share a material or differ), and a menu of tungsten, ruthenium, cobalt, copper, or aluminum for the electrodes. Pinning down those compatible material sets is most of the real work in turning “use one break instead of two” from a layout wish into a process that yields, and it is why an isolation idea this conceptually simple still warrants a detailed grant.

For the capex desk, the takeaway is about where node economics actually come from. The marketing of a node is an architecture name and a transistor count; the reality is a stack of area-reclaiming and yield-preserving techniques like this one, each shaving a little die area or rescuing a little yield. Density improvements are what make the next node cheaper per transistor and thus worth its enormous capital cost — and they are sourced from exactly these incremental, heavily-engineered process inventions. IBM’s habit of filing them ahead of volume production makes its patent portfolio a useful map of where the enabling work is happening before any foundry talks about it publicly.

The caveat we attach: a process patent is a defensive and licensing asset, not a node or a product. It evidences where a density technique was invented and the specific dummy-gate, oxidized-channel construction claimed; it does not establish who ships it or at what yield.

For the period investor, the lesson is that node leadership is an accumulation of small process wins, each one a contractual claim on a sliver of density that compounds across a design. A 2023 GAA isolation grant from IBM — reclaiming area by reusing the device’s own channels as a single-break isolator, with a fully specified set of compatible insulator, spacer, and electrode materials — is one such win: the kind the headline never mentions but the node depends on.