A published patent application is not a product and not a grant; it is an application that has cleared the roughly 18-month confidentiality window and become public. Read as a body, a company's freshly published applications are a delayed look at where its R&D was spending attention a year and a half earlier. In the week ending March 27, 2026, Kioxia — the Japanese flash-memory maker spun out of Toshiba and a leader in 3D NAND — had 21 applications published, and they sort into two tracks: the NAND business it is known for, and a sizeable cluster on memory device types that sit outside NAND entirely.

The NAND track: structure and operation

About half the published set addresses 3D NAND directly. US20260089948A1 describes a stacked memory-cell-array structure with multiple stacked sub-structures separated by an insulating third structure. US20260089912A1 describes stacked semiconductor layers connected by a via wiring with connecting electrodes on both sides. US20260088105A1 describes a read operation that raises the voltages of three interconnect layers at different rates to speed sensing, and US20260088056A1 describes a word-line and block-select wiring layout with bent select lines to ease spacing. This is the array-structure and operation engineering a NAND maker files continuously as stack counts climb — incremental, but the backbone of the storage business.

The track that points elsewhere: oxide channels and ferroelectrics

The more telling cluster is the one that is not NAND. Several applications describe transistors with an oxide-semiconductor channel — a device family associated with DRAM-style and capacitor-less memory rather than charge-trap flash. US20260090006A1 describes an oxide-semiconductor layer between two electrodes with a dual-portion gate; US20260089920A1 describes a multi-region electrode structure for such a cell containing indium, tin, zinc, tantalum, or tungsten; and US20260089916A1 describes a gate surrounding two oxide-semiconductor channels. The application text for the dual-channel cell is specific about the geometry:

The gate electrode includes a first portion and a second portion. The first portion faces the first oxide semiconductor layer and is in contact with the gate insulating layer in the second direction, and has a first length in the first direction.— Semiconductor Device And Semiconductor Memory Device, US20260089916A1

A second sub-cluster sits in ferroelectric memory. US20260090053A1 describes a charge-storage layer using hafnium- or zirconium-based crystals in specific space groups. US20260088073A1 describes a write scheme for a ferroelectric memory cell, and US20260088061A1 and US20260088057A1 describe ferroelectric memory array structures with vertical bit and source lines. Ferroelectric hafnium-oxide memory is one of the candidates the industry is studying as a denser, lower-power non-volatile cell. Filing across cell structure and write operation for it is the signature of an exploratory program, not a one-off.

A third sub-cluster covers selector and resistive-switching materials. US20260090292A1 and US20260090282A1 both describe memory cells with a switching layer of specified oxide and chalcogenide compositions stacked with a variable-resistance layer — the selector-plus-resistor structure that crosspoint and resistive memories are built on. Selectors are the device that makes a dense crosspoint array addressable, and material-composition filings on them point to work on the array type rather than the individual cell.

For a business reader, the value of the split is what it implies about where engineering was being spent. The published applications do not announce a product line, and a NAND maker files broadly. But the weight of the non-NAND cluster — oxide-semiconductor channels for DRAM-style cells, ferroelectric storage, and crosspoint selector materials, filed in the same batch — is a delayed picture of a company whose public identity is flash memory directing meaningful R&D toward device types that sit beside or beyond NAND. The oxide-channel work in particular, US20260090006A1 and US20260089920A1, describes capacitor-adjacent cell structures that the memory industry associates with the long-discussed effort to build denser embedded and standalone memory without conventional DRAM capacitors.

The usual caution holds: a published application is not a granted patent and not a product, and it indicates direction, not commercialization. What the week documents is where Kioxia's filings, dated to roughly a year and a half earlier, were pointed — toward continued 3D NAND structure and operation, and, more notably for a flash-centric maker, toward oxide-channel devices, ferroelectric cells, and crosspoint selector materials. The record reads as a NAND company keeping a hand in the memory types that sit outside its core franchise.