The capex-meets-IP fact first: transistor transitions are rarely clean breaks; foundries often run new and old device types side by side. US11575050B2, granted February 2023 to TSMC, patents a structure with both gate-all-around (GAA) and planar devices on one chip (CPC H01L 29/78696).

Gloss it once. GAA is the advanced transistor for high-performance logic, but not every circuit on a chip needs it — some functions are fine with simpler, cheaper planar devices. Building both on the same die lets a designer use the expensive transistor only where it pays off, optimizing area, power, and cost across the chip.

“An integrated circuit includes gate-all-around (GAA) nanowire transistors, GAA nanosheet transistors, and planar devices on the same substrate.”— U.S. Patent No. 11,575,050 source

The grant is more specific than a single die mixing two device families. The abstract describes three coexisting flavors on the same substrate: GAA nanowire transistors, GAA nanosheet transistors, and planar devices — a gradient of channel geometries, not a binary. It then ties those geometries to two physical dials. First, the gate dielectric: the dielectric layers of the GAA nanowire and GAA nanosheet transistors have substantially the same thickness, which is smaller than the dielectric of the planar devices. Second, channel width: the planar device channel is the widest, the GAA nanosheet channel is narrower, and the GAA nanowire channel is narrowest of all. Claim 1 makes the same point in legal language — a planar transistor whose gate dielectric “is thicker than the first gate dielectric layers” and whose channel width is larger than the GAA channels it shares the substrate with.

Read as engineering economics, that ordering is the point. A thicker gate dielectric and a wider channel are the signatures of a transistor built to tolerate higher voltage and to be cheap and robust rather than fast. The thinner dielectric and tightly wrapped channels of the GAA devices are the signatures of a transistor built for speed and low-voltage switching at the cost of process complexity. By specifying all three on one substrate, the patent describes a chip where the designer can place the expensive, fast device only on the logic that needs it and fall back to planar devices for I/O, analog, or higher-voltage functions that would gain nothing from nanosheets.

Why a capex desk reads it: this is the economics of a node transition made physical. Running two — here, three — device types means more masks, more process steps, and more integration complexity, all of which is cost. But it also means the most expensive new transistor is deployed selectively rather than across the whole die, which controls cost. The patent protects how to do that mixing manufacturably, and the dependent claims (different dielectric thicknesses, different channel widths co-fabricated on one substrate) are exactly the integration details that make selective deployment producible at yield.

The period framing matters. In 2023, GAA was ramping at the leading edge and the marketing story was a clean jump to a new transistor. A patent on coexisting with planar devices — and on grading between nanowire and nanosheet GAA within the same chip — reflects the practical reality that foundries do not flip the whole chip to the new device at once. Transitions are managed, gradual, and add engineering overhead, and the IP that governs the mixing is filed years before the marketing node is retired.

It is worth dwelling on why this is hard enough to patent. Co-fabricating a planar transistor and a stacked GAA transistor on one substrate means the same process flow must produce two different gate dielectric thicknesses and three different channel widths without separate wafers or wildly divergent step counts. The dependent claims spell that coexistence out: claim 2 adds the second GAA family (the nanosheet variant alongside the nanowire variant) with its own gate dielectric and electrode wrapping its channels, and the abstract fixes the relative dimensions — nanowire and nanosheet dielectrics “substantially the same thickness” and both thinner than the planar dielectric, with channel widths ordered planar > nanosheet > nanowire. Each of those relationships is a separate masking and deposition challenge, and bundling them into one manufacturable flow is precisely the kind of integration know-how a foundry protects.

There is also a strategic reading for a capex desk. A patent like this is a hedge against the timing risk of a node transition. If a foundry can ship products that are mostly planar with islands of GAA — or mostly GAA with planar where it is cheaper — it can monetize a half-built advanced process and migrate customers gradually rather than waiting for a fully GAA design ecosystem to mature. That flexibility is worth money during the years when the new transistor is expensive and the design tools and IP libraries are still catching up, which is exactly the window in which this 2023 grant lands.

The caveat we attach: this is a structure patent and a defensive asset. It evidences TSMC’s approach to mixed-device design and the specific dielectric-and-width relationships it claims; it does not quantify cost, yield, or which products use it. The patent tells you the technique exists and is owned, not how much of a given chip is planar versus GAA.

For the period investor, the lesson is to distrust the clean-break narrative of node transitions. A 2023 GAA-and-planar grant that explicitly grades dielectric thickness and channel width across three device types shows the messy, expensive middle ground that the marketing node glosses over — and shows that the cost of the transition is being engineered around, not eliminated.