Intel Corporation's slate in the June 30, 2026 grant drop carries a cluster of issued patents that share one substrate: glass. Read together, the grants signal where Intel is pointing its packaging effort — toward glass-core substrates as the plane on which future multi-die products are assembled. The hero of the cluster, US12672564B2 ("Technologies for vertically interconnected glass core architecture"), mounts dies above and below a glass layer around a cavity-embedded bridge die; the rest of the cluster works the same material from adjacent angles. This is a report of what the issued records disclose, not a market judgment.

The strategic tell is breadth across the packaging stack rather than a single filing. In the same issue, US12672562B2 ("Cavity-less interconnect component on glass core") covers the case where the interconnect bridge sits on a planar glass layer surrounded by mold instead of inside a cavity — a second construction route to the same die-to-die bridging. US12672559B2 ("Low insertion loss coaxial through-hole for highspeed input-ouput") is directed to a coaxial through-glass via for high-speed I/O, and US12672566B2 ("Wireless chip-to-chip high-speed data transport") reaches toward microbump-antenna wireless die-to-die links. The portfolio signals a company covering multiple physical implementations of the same glass-substrate idea in one drop. When a portfolio protects both the embedded-bridge and the on-glass-bridge route to die-to-die connection, and adds separate coverage for the vias and the wireless links that feed those dies, the pattern reads as an intent to own the construction options around glass rather than to bet on a single one.

One grant in the cluster is directed at moving components that normally live on the circuit board into the package itself. US12672239B2 ("Hybrid bonded passive integrated devices on glass core") hybrid-bonds discrete passives — inductors and capacitors — directly onto the glass core, and its abstract states the construction plainly:

An electronic device includes a substrate including a glass core layer and first contact pads on a first surface of the glass core layer; one or more discrete passive electronic components disposed on the first surface of the glass core layer, the one or more discrete passive electronic components including second contact pads on a bottom surface of the one or more discrete passive electronic components; and hybrid bonds between the first contact pads of the glass core layer and the second contact pads of the one or more discrete passive electronic components.— Hybrid bonded passive integrated devices on glass core, US12672239B2

Reading the direction

Advanced packaging is where the semiconductor supply chain has been re-pricing: capacity for stitching multiple dies together at fine pitch has become as strategically scarce as leading-edge wafers, and glass substrates are one of the routes vendors have publicly discussed for pushing past the limits of organic laminate. A grant cluster this concentrated on one material — glass cores, through-glass vias, on-glass bridges, on-glass passives, coaxial and wireless glass interconnects — is a directional signal that Intel is building out coverage of glass-based heterogeneous integration rather than treating it as a one-off. The recited features track the requirements of AI-class packages: the hero grant names high-bandwidth-memory dies as the components mounted above the glass and copper via-pillars doubling as a thermal path to a heat sink, and a companion grant addresses the coaxial via geometry that high-speed I/O needs.

Two of the interconnect grants read as answers to specific electrical constraints of these packages, which is itself a signal about the workloads Intel is designing the substrate for. The coaxial through-glass via of US12672559B2 wraps a signal via in a grounded conductor to hold down insertion loss on high-speed input-output — the kind of link a package feeding an accelerator needs. The hero grant, US12672564B2, names high-bandwidth-memory dies as the components mounted above the glass and recites copper via-pillars that double as a thermal path to a heat sink. Those are the requirements of AI-class packages, and the fact that the portfolio names them explicitly is part of the directional read: the glass work is aimed at dense, memory-adjacent, high-bandwidth assemblies rather than commodity substrates.

The same issue rounds out the picture with the thermal and device layers that dense packaging depends on. US12672256B2 ("Immersion cooling system with phoretic force particulate collection") is directed to keeping a chip package cool while immersed in a dielectric liquid, and device-level grants such as US12672347B2 ("Lower device access in stacked transistor devices") point toward the stacked, backside-connected silicon that these packages are meant to carry. The commercial read is coverage across the full assembly problem — substrate, interconnect, passives, I/O, and cooling — concentrated in a single grant drop. For a business reader watching where the advanced-packaging bottleneck gets contested, a same-day cluster this concentrated on one substrate material is the kind of portfolio footprint that marks a company treating glass as a platform rather than an experiment.

What the record shows

Every grant referenced here is assigned to Intel Corporation and issued in the June 30, 2026 B2 drop; each is an issued patent, not a pending application. Collectively they are directed to glass-core package substrates, cavity-embedded and cavity-less interconnect bridges, hybrid-bonded on-glass passives, coaxial through-glass vias, wireless die-to-die links, and the cooling and stacked-device structures around them. That concentration is the signal the portfolio sends about Intel's packaging direction. It is not a statement about market share, product timing, or which of these constructions, if any, reaches volume — only about what the issued record now covers.