When a memory maker's newly published patent applications cluster into two clean piles, the split is worth reading. In the week ending May 22, 2026, SK hynix had about ten applications published in the semiconductor area, and they divide almost evenly between two ideas of "stacking." One pile is about stacking finished dies into a package and getting test signals out of the result. The other is about stacking memory cells taller inside a single chip. A published application is not a product — it is a roughly 18-month-delayed snapshot of where R&D money went — and read that way, this batch signals a company funding both the package and the cell at the same time.

That dual emphasis tracks the structural shift in memory. The AI buildout did not just raise demand for bits; it pushed the constraint into how memory is assembled — high-bandwidth memory stacks, taller NAND, and the packaging that wires it all to a logic die. SK hynix's published filings read as a company industrializing both ends of that problem rather than picking one.

The packaging pile: stacking dies, and proving they work

The first cluster is about chip-stack packages. US20260144147A1 describes a chip-stack package with a front bump bonded to a carrier bump and a mold member surrounding the stack. US20260143722A1 covers a reverse-wire-bond method for connecting the upper dies in a stack. What stands out across the pile is how much of it concerns testing the stack. US20260144015A1 is explicit about building test access into the package itself:

The chip stack package additionally includes a test pad disposed on the mold member and connected to the second test bump.— Chip Stack Package, US20260144015A1

That sentence points at the unglamorous problem that decides whether stacked memory is sellable: once dies are bonded and molded, finding the bad one is hard, and a stack is only as good as its weakest layer. Engineering test bumps and test pads into the package is a tell that SK hynix is investing in the yield-and-reliability side of stacking — exactly where cost and salability live for high-layer memory. US20260144104A1, a semiconductor package with a recessed-electrode bump structure, fills in the interconnect detail underneath.

The cell pile: building memory taller

The second cluster moves inside the chip, to the vertical NAND cell. US20260143712A1 describes a memory device with a channel structure extending through a gate stack of alternating conductive and insulating layers into a source structure — the core architecture of 3D NAND, where memory is built up in layers rather than out across the wafer. US20260143711A1 adds a channel back-gate layer to create a second current path through the same cell. US20260143709A1 covers a device that bonds the memory-cell array onto a separate peripheral-circuit structure — the "CMOS-under-array" style of construction that frees up area as layer counts climb. The common thread is height: more bits per cell, more layers per stack, more of the chip built in the vertical dimension.

Two more applications round out the footprint on the reliability side. US20260141935A1 covers a DRAM-style test mode for screening reliability, and US20260140826A1 covers an error-correction circuit with a "poison" data pattern for flagging bad data. Both are about catching faults — the same testability theme that ran through the packaging pile, now applied to the bits themselves.

The inventor overlap reinforces that this is coordinated rather than coincidental. Several of the packaging filings share names — Wan Choon Park appears across the chip-stack and bump applications, and Min Ju Jang and Jung Hwa Lim recur on the stacking-and-test filings — which is consistent with a single program working the package problem from multiple angles rather than scattered one-off ideas. On the cell side, the run of NAND filings sits in the same publication window, pointing to a memory-architecture team filing in parallel with the packaging group. Two programs, published the same week, aimed at the two layers a memory maker has to get right at once.

Why does a two-pile split matter to anyone tracking the memory business? Because the memory roadmap now advances on two axes at once. The cell axis (taller 3D NAND, denser DRAM) buys raw capacity per chip. The package axis (die stacking, bonding, test access) buys the ability to assemble those chips into the high-layer stacks that AI systems consume — and to do it at a yield that pays. A maker strong on one axis and thin on the other has a gap a rival can exploit. SK hynix's published filings show R&D flowing into both axes in the same week, with testability woven through both, which is the signal that the company is treating assembly and reliability as first-class problems rather than afterthoughts.

The caveats are the standard ones for applications, and they cut both ways. These are publications, not grants; the claims can narrow before any patent issues, and a filed idea is not a shipping process. The roughly 18-month publication lag also means this work reflects spending decisions from around 2024, not a live readout of today's line. But the pattern is what carries the weight here: a coordinated set of filings spanning stacked packages, built-in test access, 3D-NAND channel construction, array-to-periphery bonding, and DRAM reliability is the footprint of a memory maker investing across the full assembly-and-reliability stack — the parts that decide whether high-density memory can actually be built and sold, not just designed.