The capex-meets-IP fact first: an increasing share of a chip product’s value and engineering effort now lives in the package, not the die. US12283577B2, granted April 2025 to Samsung, patents a fan-out semiconductor package (CPC H01L 25/16).

Gloss it once. In fan-out packaging, the die is embedded and its connections are “fanned out” into a redistribution layer built around it — allowing more connections in a smaller, thinner package with better electrical performance, which is why it spread from mobile into high-performance applications.

“A fan-out semiconductor package includes: a package body including a fan-in area corresponding to a through-hole located therein, a fan-out area surrounding the fan-in area, and a body interconnect structure arranged in the package body corresponding to the fan-out area.”— U.S. Patent No. 12,283,577 source

The grant is more than “a fan-out package.” Its central idea, per claim 1, is a package body with a through-hole into which a multi-chip “fan-in chip structure” is dropped: a first chip, a capacitor chip spaced apart from it, and a second chip disposed across the tops of both. Around that fan-in region sits a fan-out area with a body interconnect structure, a redistribution structure on the bottom routing signals out to the fan-out area, and interconnect vias on top. The package is built to embed a small heterogeneous stack — logic, a companion die, and a dedicated capacitor — inside the board itself and then redistribute its I/O outward.

The capacitor chip is the tell. Claim 3 specifies it is a trench capacitor or a through-via capacitor, and several claims (5–8) describe through-vias in both the first chip and the capacitor chip connecting up to the second chip’s pad and out to the redistribution element. Integrating a deep-trench or through-silicon-via capacitor right next to the logic die, inside the package, is a power-integrity move: it puts decoupling capacitance physically close to where the current is drawn, which matters for high-speed, high-current parts. Claim 18 then stacks the whole thing into a package-on-package assembly — a lower package carrying the fan-in chip structure with an upper package and its own semiconductor chip mounted on top — so the patent reaches from die-in-board integration up to stacked-package products.

Why a capex desk reads it: fan-out is a capital-intensive packaging capability, and owning competitive fan-out IP lets a company capture margin in the packaging step rather than ceding it to specialized assemblers. The specifics here — embedding a capacitor chip with through-vias for power integrity, supporting package-on-package stacking — are exactly the value-added features that let a vertically integrated maker like Samsung defend end-to-end value rather than selling a bare die into someone else’s package.

The period framing matters. By 2025, advanced packaging was a recognized value center and a capacity bottleneck. A Samsung fan-out grant that goes beyond redistribution to integrate decoupling capacitance and stackability reflects continued investment in owning the packaging layer where product value — and the capital to build it — increasingly concentrates.

The construction details in the dependent claims show why this is a packaging-as-product story rather than a generic redistribution patent. The fan-in chip structure is encapsulated in stages — a first encapsulation layer placed between the first chip and the capacitor chip, then a second encapsulation layer sealing the whole structure inside the through-hole (claim 9). Claim 13 specifies that the top surfaces of the first chip, capacitor chip, and second chip are the active surfaces while their bottoms are inactive, and claim 16 has the first chip and capacitor chip overlapping the second chip in plan view. That is a deliberately engineered face-to-face stack: two lower dies (logic plus a dedicated capacitor) presenting their active sides up to a die that bridges across both, with through-vias carrying signal and power down to the redistribution layer. The body interconnect structure even maintains equal width top-to-bottom (claim 19), a manufacturability constraint that matters for building tall, reliable interconnect through the package body.

For a capex desk, the strategic content is that this kind of package captures functions that used to be discrete components. A trench or through-via capacitor embedded beside the logic die replaces a separate decoupling capacitor on the board and improves power delivery at the same time; package-on-package stacking lets a memory or companion package ride on top without a larger footprint. Each of those is value that migrates from the board level and from specialist assemblers into the package the chipmaker controls. Owning the IP for that integration is how a vertically integrated maker keeps the margin from advanced packaging in-house instead of paying it out to an OSAT.

The caveat we attach: this is a packaging-structure patent and a defensive asset. It evidences Samsung’s fan-out IP position and the specific embedded-capacitor and package-on-package structures it claims; it does not quantify capacity, cost, or which products use it.

One more structural detail underscores the “package as product” reading. Claim 4 notes that the second chip’s pad has a different structure than the connection pads on the capacitor chip and first chip, and claims 5 through 8 route that second-chip pad to the through-vias of both lower chips and on to the redistribution element. In other words the bridging die is wired as the integrating layer that ties the logic and the capacitor together and out to the board, while the package body’s own interconnect structure carries the fan-out signals with first and second interconnect pads on its bottom and top surfaces (claim 10). The result is a self-contained subsystem — multiple dies, embedded passives, and a built-in interconnect spine — that behaves like a single component, which is exactly the kind of consolidation that lets the package, not the bare die, define the product a customer buys.

For the period investor, the durable point is that the package has become the product in a meaningful way — here, a package that swallows a capacitor and a second die and still fans the I/O out cleanly. A 2025 fan-out grant is a marker of where the value, and the capex, has migrated.