In the U.S. patent grant cycle dated April 7, 2026, Micron Technology (MU) was issued 27 patents that surface under a broad semiconductor search, and read together they trace a coverage map across the company's core memory franchise rather than one marquee invention. The grants concentrate in three CPC neighborhoods: DRAM cell and array operation (G11C), three-dimensional NAND structure (H10B), and the controller logic that sits between a host and the memory (G06F). For a company whose business is selling DRAM and NAND into data-center, mobile, and automotive sockets, a grant is enforceable coverage of the methods that make those parts work and keep their data intact.

What the grants cover

The most defensively interesting record in the batch addresses the row-hammer problem, the disturb mechanism by which repeatedly activating one DRAM row can flip bits in its neighbors. US12597459B2, "Apparatuses and methods for row hammer counter mat," claims a memory array that dedicates a counter mat to track per-row access counts and trigger a targeted refresh of victim rows. Row-hammer mitigation has migrated from an academic curiosity to a mainstream reliability requirement as DRAM cells shrink, and the grant places Micron's counter-mat approach inside enforceable claim language.

A second data-integrity grant, US12596610B2, "Parity data in dynamic random access memory (DRAM)," describes generating parity at a controller and storing that parity in a DRAM device while user data is written to a separate non-volatile device, then reading both back through the controller. The claim ties parity placement to the DRAM tier specifically, a method-level position on how error-correction data is distributed across a mixed memory system.

On the NAND side, US12598742B2 covers a method of forming a memory array with vertically alternating tiers and channel-material strings in channel openings, the structural backbone of 3D NAND scaling. The abstract describes the sequence directly:

Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches.— Memory array comprising strings of memory cells and method used in forming a memory array comprising strings of memory cells, US12598742B2

Two further grants extend the array-management footprint. US12596646B2 claims managing multiple erase blocks coupled to a same string and routing write data by a determined temperature classification, while US12597472B2 covers selectively erasing one of those erase blocks using gate-induced drain leakage. Both are operational methods that govern how NAND blocks are written and erased, the kind of coverage that touches firmware behavior across a product line.

The controller layer

A large share of the week's grants sit not in the memory cell but in the controller and interface logic around it. US12596668B2 claims a dual-interface high-speed memory subsystem that exposes a boot partition over a serial interface and a user partition over a separate high-speed interface. US12596389B2 covers thermal management for memory sub-systems, using a phase-change material with a melting point between ambient and the thermal-throttling threshold to extend the window before throughput is limited, a directly commercial concern for SSDs and modules operating in hot, low-airflow enclosures. Additional grants in the batch address logical-to-physical mapping compression, parity buffering across channels, and protocol-layer reset, all controller-resident methods.

Mapped against the rest of the cycle, the volume itself is the signal. In the same April 7 grant set, the leading semiconductor-tagged assignees by issued-patent count included International Business Machines, Samsung Electronics, Intel, and Taiwan Semiconductor Manufacturing; Micron's 27 grants place it among the most active memory-specific filers for the week. The claims span the full stack a memory maker controls, from the physical cell and its disturb defenses up through erase logic and host-facing interfaces.

For a general reader, the business reading is straightforward: a granted claim is coverage a company can assert, and the surrounding cluster shows where it is concentrating that coverage. This batch indicates Micron is building enforceable positions less around a single device geometry and more around the reliability and management methods, refresh defenses, parity placement, thermal behavior, erase control, that determine how its DRAM and NAND perform in the field. Those are the same attributes data-center and automotive buyers specify, which is what makes method-level memory patents commercially relevant rather than merely technical. The record does not tell us how broadly any one claim will read in practice; it does show the areas where Micron now holds issued coverage.