The capex-meets-IP fact first: advanced packaging is not only about density — it is about reliability, because field failures and yield loss are real cost centers. US12347802B2, granted July 2025 to TSMC, patents removing die corners to suppress underfill cracks (CPC H01L 24/20).

Gloss it once. Underfill is a material injected between a die and its substrate to mechanically support the connections. As the package heats and cools, mechanical stress concentrates at the die corners, where the underfill can crack — leading to failures. Removing or shaping the die corners relieves that stress concentration, suppressing the cracks.

“A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure.”— U.S. Patent No. 12,347,802 source

The patent is, at heart, about geometry — specifically chamfer geometry — and the claims are unusually physical about it. The fan-out package has its die set in an epoxy-molding-compound die frame with a redistribution structure on top. The invention forms “chamfer regions” at the corners: angled surfaces that connect the package’s horizontal and vertical faces and are, by repeated definition in the claims, “not horizontal and not vertical.” When the package is later attached to a substrate and underfilled, the underfill “laterally surrounds and contacts an entirety of the angled surfaces” (claim 14). The sharp 90-degree corner where thermal stress would otherwise spike is simply gone — replaced by a beveled or convex ramp that spreads the load.

What makes it a process patent rather than a shape claim is how the chamfers are made. Claim 1 walks through a full reconstituted-wafer fan-out flow — forming a 2D array of dies in an EMC matrix, building the redistribution layer, attaching solder, detaching the carrier, and dicing — and then removes corner portions of the redistribution structure and EMC die frame after dicing to create the chamfers. Claim 2 gives two manufacturing options: a bevel cut that yields “planar beveled surfaces” or a grinding process that yields “convex surfaces.” Claim 9–10 describe an alternative where the chamfers are formed before dicing as a 2D array of “diamond-shaped openings at corners of die areas” in the reconstituted wafer, with the dicing channels running through them. Either way the patent ties the stress-relieving shape to a specific, yield-friendly point in the packaging line.

Why a capex desk reads it: reliability defects in advanced packages cause yield loss in the fab and, worse, failures in the field that carry warranty and reputational cost. A foundry that owns crack-suppression IP — and owns more than one route to it, before or after dicing, by bevel or by grind — protects the economics of its packaging business on both ends. This is reliability as a cost-control investment, engineered into the dicing-and-underfill flow rather than bolted on as a feature.

The period framing matters. By 2025, advanced packaging was central to high-value products, and reliability under thermal cycling was a serious concern for dense, high-power assemblies where corner stress is most punishing. A TSMC crack-suppression grant that specifies the chamfer geometry and multiple ways to manufacture it reflects the maturation of packaging from “can we build it” to “can we build it reliably at yield.”

The breadth of the manufacturing options in the claims is what makes this a strong defensive asset rather than a narrow trick. The patent covers chamfering after dicing (claim 1), forming the chamfers before dicing as discrete recess cavities so the dicing channels pass through them (claims 8–9), and a convex chamfer with a taper angle that varies with distance from the underfill interface (claim 12) — a shape tuned so the stress relief is greatest right where the underfill meets the package. It also reaches the case where a single chamfering or etching step simultaneously removes corner material from both the EMC die frame and the redistribution structure, forming one angled surface that spans both (claims 5, 17). By claiming bevel and grind, before-dice and after-dice, and combined-layer chamfers, the patent fences off the practical ways a competitor might try to relieve the same corner stress.

For a foundry whose advanced-packaging business is now a material part of its value, that breadth is the point. Thermal cycling in dense, high-power packages drives mechanical stress into corners, and underfill cracks there translate into field returns, warranty exposure, and reputational damage with the marquee customers that buy leading-edge packaging. Owning a wide patent on the cheapest reliable fix — a shaped corner formed in the existing dicing-and-underfill flow — protects margin on both the yield side and the field-reliability side. It is a reminder that in advanced packaging, reliability engineering is not an afterthought but a line of defense for the economics of the whole product.

The caveat we attach: this is a packaging-reliability patent and a defensive asset. It evidences TSMC’s focus on package reliability and the specific chamfer-formation methods it claims; it does not quantify yield or failure-rate improvement.

For the period investor, the durable point is that packaging reliability is a quiet cost center, and the IP that controls it protects margin on both the yield line and the warranty line. A 2025 underfill-crack grant — trading a stress-concentrating sharp corner for a manufacturable chamfer, claimed across bevel and grind, before-dice and after-dice variants — is a marker of that less-visible side of the packaging business, where the hardest engineering is spent making the package survive being used.