Taiwan Semiconductor Manufacturing Company (TSMC) is one of the densest patent filers in semiconductors, so the question on any given pub-drop day is not whether the foundry published but where the applications cluster. On June 25, 2026, the answer is unusually legible. The drop carries 32 published applications assigned to TSMC across its assignee-name variants, and the classifications concentrate in two places: backside power delivery and the transistor structures around it, and wafer-level / 3D packaging. Those are precisely the layers that gate advanced-node interconnect and AI-accelerator assembly — the parts of the stack where, in TSMC's own filing footprint, the disclosed engineering is being directed.

The application that anchors the backside-power side of the drop is titled "Semiconductor Device and Fabrication Method Thereof" (US20260182362A1). It is directed to a transistor whose front-side circuit structure connects to the gate while a separate backside circuit structure carries a metal-insulator-metal (MIM) capacitor and a power line. In commercial-roadmap terms, that is backside power delivery stated plainly: the power and decoupling network is moved to the wafer's backside, freeing the front side for signal routing. Independent claim 1 describes the arrangement directly.

A semiconductor device, comprising: a semiconductor structure comprising a semiconductor transistor; a front side circuit structure, disposed over and electrically connected to a gate structure of the semiconductor transistor; and a backside circuit structure, disposed on a backside of the semiconductor structure, wherein the backside circuit structure comprises a metal-insulator-metal capacitor and a power line electrically connected to the metal-insulator-metal capacitor.— Semiconductor Device and Fabrication Method Thereof, US20260182362A1

The backside theme repeats across the drop rather than appearing once. Two companion applications place memory functions on the backside: a "Backside Anti-Fuses" disclosure describes a one-time-programmable circuit on the backside of the device coupled to a frontside anti-fuse control cell (US20260181884A1), and "Semiconductor Memory Devices With Backside Transistors" describes a memory cell whose programming and reading transistors sit on opposite faces of the substrate, joined by a backside via (US20260181883A1). When power lines, decoupling capacitors, anti-fuses, and even transistors are each being disclosed on the wafer backside in the same week, the recurrence is the signal: TSMC's disclosed work is exercising the backside as an active circuit plane, not just a power-routing afterthought.

The packaging side: fan-out, intermediary structures, and lids

The second concentration in the drop sits in wafer-level and 3D packaging, captured in the H10W package classifications. "Semiconductor Package and Method of Manufacturing the Same" discloses a fan-out structure in which a die is laterally encapsulated and a redistribution structure with dielectric and metallic layers carries bumps, with undercut cavities engineered beside the metallic pads (US20260182402A1). "Package Structures and Manufacturing Method of the Same" describes an intermediary structure of conductive pillars in an encapsulant bridging a first semiconductor structure embedded below to a second structure stacked above (US20260182398A1) — the vocabulary of stacked, vertically interconnected dies. A third, "Package Structure and Method of Forming the Same," is directed to a package with a molding layer, a thermal interface material, and a lid adhered through the TIM (US20260182447A1), the thermal-management layer that high-power accelerator packages depend on.

For a money-desk reader the relevant point is not any one of these structures but the composition. The same-week portfolio interlocks backside power delivery on the device side with fan-out redistribution, vertical intermediary interconnect, and lid/TIM thermal management on the assembly side. Those are the two halves of advanced-node interconnect: getting power and signal in and out of the transistor efficiently, and getting heat and I/O in and out of the stacked package. The applications do not disclose revenue, capex, capacity, or customer commitments, and nothing here should be read as a winner-versus-rivals verdict; they are pending publications, not grants, and TSMC files at high volume. What the classification mix attributes is engineering intent — the disclosed effort is concentrated where leading-edge logic and AI-accelerator packaging actually bottleneck.

What the classification concentration shows

Reading the drop by CPC makes the direction explicit. The transistor-side applications cluster in the H10D nanosheet and gate classes — "Method of Manufacturing a Semiconductor Device and a Semiconductor Device" works a wall-fin structure for gate-all-around stacks (US20260182005A1), and "Stacked Device Having Stacked Dielectric Structures With Different Stresses" describes top-over-bottom transistor stacking (US20260181951A1), the complementary-FET direction that pairs naturally with backside power. The packaging-side applications cluster in H10W. The most frequent single CPC subclass in the drop is H10D 30/6735 (gate-all-around nanosheet device work), and H10W package classes recur across the fan-out and intermediary-structure filings. The concentration is the read: leading-edge transistor architecture and wafer-level/3D packaging, the two layers TSMC's advanced-node and AI-accelerator business runs through.

The signal worth marking is one of direction, grounded in the filing record rather than in any roadmap claim. In a single week, TSMC published a coherent set of applications that move power, decoupling, memory, and even transistors onto the wafer backside, and a parallel set that builds the fan-out, vertical-interconnect, and thermal-lid machinery of advanced packaging. The lead application states the backside-power arrangement in its independent claim; the packaging applications state the assembly side in theirs. None of this is a judgment on breadth, strength, or whether any application will issue. But for tracking where a high-volume foundry is pointing its disclosed engineering, the June 25 drop reads forward toward advanced-node interconnect and packaging — and that is the layer the foundry's leading-edge economics ultimately run through.