Taiwan Semiconductor Manufacturing (TSM) was issued a dense cluster of advanced-packaging patents on a single grant date, June 2, 2026. The records describe coverage in the redistribution and die-to-die interconnect layers — the part of the chip that is no longer about transistor size but about how separate dies are stitched together inside one package. For a general reader, that is the layer where the economics of AI accelerators increasingly live: the logic die, the high-bandwidth memory stacks beside it, and the wiring between them.

To put the cluster in plain terms first: a modern AI accelerator is rarely a single chip. It is a logic die — the processor — surrounded by stacks of high-bandwidth memory, all sitting on a thin layer of silicon or built-up wiring called an interposer or redistribution structure, and the whole assembly is then encapsulated into a package that mounts to a board. The redistribution layer is the dense local wiring that carries signals between those dies; a local-interconnect or bridge die is a small piece of silicon embedded to shorten the highest-traffic die-to-die paths. These are the structures the June 2 grants describe, which is why a packaging grant cluster, rather than a transistor one, is the relevant record for following where assembly value is accruing.

The grant batch is broad. US12648478B2, "Package structure and method for forming the same," describes a package component over a redistribution structure with a controlled underfill geometry. US12648464B2 covers a multi-die package whose redistribution layer carries vias with an "elliptical-like shape" where they overlap the dies. And US12648452B2 covers a package with a local interconnect component embedded in a redistribution layer, electrically coupling two integrated-circuit dies — a description that maps onto the bridge-die approach now central to lateral chiplet integration.

What the records describe

The same date carried adjacent grants. US12648441B2 describes an electrocaloric heat-dissipation structure placed near a hot spot in a power-management IC "particularly useful when the PMIC is in a 3D package" — thermal management being one of the recurring constraints in stacked silicon. Read together with the redistribution and interconnect grants, the issued claims sit across the assembly steps of a modern multi-die package rather than at any single point.

The footprint extends past June 2. In the surrounding grant window, the same assignee was issued US12648498B2, covering surface treatment in an integrated-circuit package where two dies are joined with "dielectric-to-dielectric bonds and metal-to-metal bonds" — the hybrid-bonding interface that allows dies to be stacked with very fine pitch. A further grant, US12648493B2, describes wafer-on-wafer and chip-on-wafer-on-wafer bonding methods, explicitly framed around reducing "manufacturing cost and cycle time." The records reach the tooling layer as well: US12648472B2 describes a bonding tool that uses a liquid-filled bag rather than a gas airbag to deform a wafer during bonding, with the stated aim of reducing run-out variation and increasing yield.

Reducing run-out variation conserves wasted wafers by increasing yield and reducing a quantity of non-functioning devices that are produced.— Semiconductor bonding tool and method of operating the same, US12648472B2

That quote points to the business context underneath the technical claims. Advanced packaging is yield-sensitive and capacity-constrained, and several of these records are framed not around novel device physics but around manufacturability — fewer scrapped wafers, lower cycle time, controlled bonding. The grants describe coverage of how the package is built, not only what it contains. The same surrounding grant window adds records that fill in the rest of the assembly path. US12648496B2 describes a package-on-package structure with two packages bonded by conductive connectors and a shaped underfill running up the sidewall — the stacking approach used when one packaged component is placed atop another. US12648495B2 describes a package integrating an antenna substrate structure over a die through a redistribution layer, with two antenna types whose polarizations are perpendicular — an antenna-in-package design for radio-frequency products. And US12648436B2 describes a device with an inductor formed within the bonding layers between two bonded dies, building a passive component directly into the die-to-die interface. Each is a different product context — stacked logic-plus-memory, RF, integrated passives — but all describe the same underlying move: putting more function into the package layer. Several records in the cluster also reach the on-die interconnect and front-end of line, showing the coverage is not confined to the back end. US12648435B2 describes an air-gap seal for an interconnect air gap, a structure used to lower capacitance and resistance in the wiring between transistors. US12648216B2 describes a method for forming a fin-based device structure with a dummy gate and selectively implanted spacer, explicitly referencing nanosheet, nanowire and gate-all-around configurations. The breadth across both the transistor layer and the packaging layer is itself a fact a reader can note: the issued claims span from the device up through the finished module.

Where the coverage sits relative to rivals

The same June 2 grant cycle included packaging patents from other assignees, which is the comparable activity a business reader can weigh as fact. Intel Corporation (INTC) was issued US12648077B2 on reduced-z-height integrated-circuit packages with nested die cavities. Advanced Semiconductor Engineering, an outsourced assembly and test provider, was issued US12648484B2 on a conductive-plate electronic device. And Infineon Technologies (IFX) received US12648456B2 covering an embedded electrical conductor between semiconductor-die pins. By raw count in the grant cycle's assignee facets, TSMC's name variants together led the named packaging-relevant grants, with Micron Technology (MU) leading overall on the strength of a memory-device cluster.

What the records map is a body of issued, enforceable coverage concentrated in the redistribution and die-to-die interconnect layers — exactly the layers that gate how a logic die talks to the memory stacked or placed beside it. The grants describe the steps of building those structures and the tooling to build them at yield. They do not, on their own, settle any competitive question; they describe what one assignee has now locked in, on one grant date, across a part of the stack that has moved from a back-end afterthought to a front-line bottleneck.