The US Patent and Trademark Office issued International Business Machines Corporation a patent on July 21, 2026 covering a chip wired in the opposite direction from where the leading-edge logic industry has been heading. US12690445B2, titled "Semiconductor device including backside signal wiring and frontside power supply," claims a device in which the metal on the front of the wafer is given over almost entirely to power delivery, while the wiring on the back of the wafer carries almost all of the signal traffic. The named inventors are Ruilong Xie, Chanro Park, Juntao Li, Min Gyu Sung and Julien Frougier.

The inversion is the point. The dominant industry approach, generally described as backside power delivery, moves the power distribution network to the back of the wafer so that the frontside metal stack can be freed up for signal routing. The granted claim describes the mirror image of that arrangement. Claim 1 recites a transistor located in the frontside of the device, a frontside back-end-of-the-line structure containing frontside metal wires, and a backside back-end-of-the-line interconnect structure containing backside metal wires, and then imposes a numeric split on which wires do what.

That split is what makes the claim measurable rather than descriptive. Rather than claiming a general architecture, the patent sets a quantified threshold on both sides of the wafer at once:

wherein at least 90% of the frontside metal wires are power distribution metal wires and at least 90% of the backside metal wires are signal wires— Semiconductor device including backside signal wiring and frontside power supply, US12690445B2

The abstract describes the same arrangement and does not diverge from the claims: it states that at least 90% of the frontside metal wires are power distribution metal wires and at least 90% of the backside metal wires are signal wires, matching the operative language of claim 1. Dependent claim 18 narrows the device to a nanosheet transistor built from a vertical stack of suspended semiconductor channel material nanosheets, with the gate structure wrapping around each nanosheet in the stack — the gate-all-around geometry that Intel, Samsung and TSMC have all moved to at their most advanced nodes. The record is classified under CPC H10W 20/427, the backside-interconnect group, along with H10D 30/6735 and H10D 30/6729 on the nanosheet device side.

The cluster issued alongside it

The grant did not arrive alone. IBM was the second-highest-volume semiconductor assignee in the July 21 issue with 26 records, and a large share of them sit in the same backside-and-nanosheet territory. US12690244B2, "Deep backside power rail cut," claims a nanosheet structure with a backside cut dielectric separating an NFET source drain region from a PFET source drain region. US12690435B2, "Self-aligned contact based via to backside power rail," covers the via geometry connecting the device layer down to that rail. US12690443B2, "Self-aligned backside contact with increased contact area," is directed to widening the bottom source drain contact beyond the width of the source drain it serves.

A fourth record, US12690246B2, "Semiconductor contact area matching," addresses the frontside and backside contact areas of the same source/drain region and claims a structure in which inner spacers control the backside contact area so that it matches the frontside one. Read together, these four cover different parts of a single problem: getting current and signal through the back of a wafer that has been thinned to the point where the transistors are reachable from both sides. IBM also took coverage further afield in the same issue — US12690186B2 claims a structure with a DRAM array on the frontside of a substrate and a second DRAM array on the backside, and US12690243B2 claims cross-coupling connections between pairs of stacked field-effect transistors.

The inventor rosters overlap heavily. Ruilong Xie is a named inventor on the hero patent and on all six of the other records cited here; Julien Frougier, Min Gyu Sung, Kisik Choi and Juntao Li recur across the set. That concentration indicates a single research group producing coverage across an interconnect problem rather than scattered filings from unrelated teams.

Why the coverage sits where it does

IBM does not manufacture leading-edge logic for merchant sale. What it holds in this area is the patent position itself, which it monetizes through licensing and through joint development work with the companies that do run the fabs. That makes the composition of an issued portfolio the relevant business asset, and it makes claims like this one — framed around a measurable property of a finished device rather than around a process recipe — the kind that can be assessed against a chip after it ships.

The wiring inversion also has a commercial logic behind it that the classification hints at. Power distribution wires are typically wide and thick to carry current with low resistance; signal wires are fine and dense. Putting the wide power metal on the frontside, where the process is mature and the layers are already thick, and pushing the dense signal routing to the backside is a different set of manufacturing tradeoffs than the industry's current direction. Whether any fab adopts it, the granted claim now covers the 90/90 configuration in a device that also meets the nanosheet limitation of claim 18.

The practical read for anyone tracking freedom to operate in advanced logic interconnect is that the July 21 issue added a claim describing a backside arrangement that the prevailing roadmaps do not use, held by a company that supplies IP rather than chips, surrounded by a same-day cluster covering the backside contacts, rails and vias that the prevailing roadmaps do use. The independent claim in US12690445B2 is a device claim, not a method claim, and it is now issued rather than pending.