Patent applications published on April 2, 2026 and assigned to Intel (INTC) read as a coherent statement of where the company is spending its silicon research. Because a published application is a roughly 18-month-delayed view of a filing, this batch is a forward-looking signal, not a record of shipping product. The 25 applications cluster in three areas: the next generation of transistor structure, the packaging substrate that carries those transistors, and integrated silicon photonics. For a company mid-turnaround on its process roadmap, the filings show which technical bets the R&D organization was placing about a year and a half ago.

The transistor cluster

The most distinctive filing is US20260096145A1, "Forksheet transistors with wrapped-around gate dielectric." A forksheet is a structure that places two transistors on opposite sides of a dielectric wall, packing them closer than separate gate-all-around devices allow; the application describes forming that dielectric spine before the gate. The abstract sets out the arrangement:

A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions.— Forksheet transistors with wrapped-around gate dielectric, US20260096145A1

Forksheet is widely understood as a candidate successor to first-generation gate-all-around nanosheets, so a filing on it indicates Intel is researching beyond its current transistor generation. The same direction shows up in US20260096146A1, which integrates gate-all-around transistors with backside power delivery on a silicon-on-insulator substrate, pairing two leading-edge ideas, GAA and backside power, in a single device. US20260096140A1 adds self-aligned backside vias formed with an endpointed subfin etch, and US20260096120A1 describes selectively removing nanoribbons to widen ribbon-to-ribbon spacing so a thicker gate dielectric can fit. A further filing, US20260096162A1, covers an arsenic-doped source/drain with a phosphorus-doped contact region to control dopant diffusion. These are the granular structural and doping choices that distinguish one node from the next.

Packaging and photonics

The second cluster is advanced packaging, and specifically glass-core substrates. US20260096459A1 describes a hybrid glass-core package with metal vias through a glass layer and a non-linear edge sidewall acting as a 3D locking mechanism, while US20260096454A1 covers through-glass vias with caps, formed by bottom-up plating so the via can move relative to the core and reduce cracking during thermal cycling. Glass substrates are an industry-watched direction for large, high-density packages, and the filings show Intel working the manufacturability details, via formation, capping, and crack mitigation, rather than the concept alone.

A third cluster is silicon photonics. US20260095026A1 and US20260095022A1 describe hybrid III-V-on-silicon optical devices with, respectively, oxide-based current confinement and a high-refractive-index spacer between the gain medium and the waveguide, and US20260095016A1 covers an on-die photon-pair source for quantum applications. Alongside these, the batch includes memory-structure filings on stacked ferroelectric RAM (US20260096103A1) and a ferroelectric/antiferroelectric capacitor-and-diode memory array (US20260094635A1).

For a general business reader, the signal is about emphasis. The published cluster indicates Intel is investing in transistor architectures beyond its current generation, forksheet, backside power on SOI, nanoribbon tuning, while simultaneously filing on glass-core packaging and on-die photonics, the interconnect technologies that matter when chips are assembled into large multi-die systems. In the same April 2 publication cycle, Intel was among the most active semiconductor-tagged filers, with its 25 applications appearing alongside comparable counts from Taiwan Semiconductor Manufacturing and Samsung; competitors are visibly filing in the same structural neighborhoods, which is the appropriate context for reading any one company's direction. These applications point to where Intel's R&D was directed; they do not establish that any structure will reach production, and an application is not an enforceable grant. What the record supports is that Intel's filings, as published, span the full leading-edge stack from transistor to package to optical interconnect.