The moat fact first: DRAM has used essentially the same one-transistor, one-capacitor cell for decades, and any rethink of that fundamental structure is a potential reset of the whole density race. US12362004B2, granted July 2025 to IBM, patents a scaled two-transistor (2T) DRAM cell (CPC G11C 11/4096).
Gloss it once. The classic DRAM cell stores a bit as charge in a tiny capacitor, gated by one transistor. The capacitor is the hard part to scale — it must stay large enough to hold a reliable charge. A 2T cell uses two transistors and rethinks how the bit is stored and accessed, potentially sidestepping the capacitor-scaling wall that limits conventional DRAM.
Why a moat read cares: IBM is a research-and-IP institution that often invents the structures the merchant makers later adopt or license. Foundational cell-architecture IP is the deepest kind of memory moat — it sits below the process, at the level of how a bit is fundamentally stored. Owning it early matters disproportionately.
The period framing matters. By 2025, conventional DRAM scaling was clearly constrained, and the industry was exploring structural alternatives. An IBM 2T-DRAM grant at that moment reflects research into a post-conventional cell — exactly where the next memory moat might be staked.
The caveat we attach: this is a cell-architecture patent and a defensive/licensing asset. It evidences where the rethink is being invented; it does not establish commercialization or that any maker will adopt it.
For the period investor, the durable point is that the deepest memory moats are at the cell level, and they are being explored now. A 2025 scaled-2T-DRAM grant from IBM is a marker of where a genuine density reset could originate.