A published patent application has cleared the roughly 18-month confidentiality window; it is public, but it is neither a granted patent nor a product. What a week's worth of a company's published applications offers is a delayed picture of where its engineering was pointed about a year and a half earlier. For TSMC (TSM), the world's largest contract chipmaker, the applications published in the week ending May 1, 2026 are dense with the packaging and transistor work the foundry files constantly. One cluster within them stands out as a directional signal: applications about getting heat out of stacked dies and advanced packages.

Cooling treated as a packaging problem

The clearest marker is US20260123405A1, which describes an integrated-circuit die stack with heat-dissipation enhancement structures. In the described arrangement, stacked dies have extension portions reaching horizontally outward, thermally conductive features are formed in those extensions, and a thermally conductive structure is embedded in the encapsulant between dies. The application states the structure directly:

A thermally conductive structure is embedded in the encapsulant layer, extending vertically between the extended semiconductor die and the extended top semiconductor die, and contacting the thermally conductive features.— INTEGRATED CIRCUIT DIE STACK WITH HEAT DISSIPATION ENHANCEMENT STRUCTURES, US20260123405A1

A companion application, US20260123406A1, describes a package structure with a heat-transfer feature formed in the redistribution structure's dielectric layer, electrically isolated from the conductive routing, that partially overlaps the die from a top view. The two applications share inventors and approach the same problem from different parts of the package — one inside the die stack, one in the redistribution layer beneath it. For a business reader, the operative point is the framing: heat removal here is designed into the packaging itself rather than handled entirely by an external heatsink. As stacked dies and high-power accelerators concentrate more heat in less volume, treating thermal paths as part of the package design is a meaningful place for a foundry to be spending engineering, because advanced packaging is the part of the supply chain where capacity and capability have become the binding constraint. The geometry in US20260123405A1 is specific about this: the dies in the stack have extension portions that reach outward, the thermally conductive features sit in those extensions, and the embedded structure in the encapsulant bridges between them vertically. That arrangement creates a heat path that does not rely solely on conducting through the active silicon, which is exactly the constraint a tall die stack runs into — the dies in the middle have the hardest time shedding heat. A redistribution-layer heat-transfer feature, as in US20260123406A1, attacks the same problem from below the stack. Two filings approaching in-package heat from different directions in one week is the kind of pattern that reads as a sustained effort rather than a one-off idea.

The packaging continuum around the thermal work

The thermal cluster sits inside a broader wave of advanced-packaging filings. US20260123529A1 describes an integrated fan-out package with a redistribution structure and an under-bump metallization pattern, and US20260123528A1 describes a package with an interposer carrying a memory die alongside other dies, using a dummy die and molding layer to match dimensions. US20260123527A1 describes a redistribution structure with a stacked-via structure using diffusion layers, and US20260123443A1 describes alignment-mark and underfill handling in a redistribution-based package. This is the fan-out and interposer vocabulary that underlies the advanced packaging used for AI silicon, and publishing thermal-management applications in the same week as this packaging work indicates the foundry is treating heat as one more variable in the same package-design effort rather than a separate discipline. The interposer filing in US20260123528A1 is notable for placing a memory die alongside other dies on the interposer and using a dummy die and molding layer to match its dimensions — the kind of layout detail that matters when memory and logic share a package, which is the defining arrangement of AI accelerators. That the same publication batch carries both this memory-on-interposer work and the heat-dissipation filings is consistent with a foundry designing the thermal solution and the die layout together, because where the memory sits relative to the logic is itself a thermal decision.

Front-end work continues in parallel

The same week's published applications also include transistor-level work, confirming the foundry is filing across the stack at once. US20260123044A1 describes a structure with stacked transistors — semiconductor nanostructures arranged one above another with separate upper and lower gate electrodes and gate-isolation structures between them. US20260123022A1 and US20260123036A1 describe nanostructure gate arrangements with dielectric wall and isolation features between adjacent gate structures. These are the gate-all-around and stacked-device building blocks of leading-edge logic, published alongside the packaging and thermal filings — a reminder that the foundry's R&D spans the transistor and the package in the same publication batch. The stacked-transistor structure in US20260123044A1, with separate upper and lower gate electrodes around nanostructures arranged one above another, is the front-end echo of the back-end stacking theme: density gained by building vertically. Seen across the week, the published applications describe a foundry pursuing vertical integration at both ends of the stack — stacked transistors in the logic and stacked dies in the package — and, with the heat-dissipation filings, building the thermal paths that vertical density demands.

The usual caution applies. A published application is not a granted patent and not a product; it points to direction, not commercialization, and no single filing confirms what will ship. What the week documents is where TSMC's filings, dated to roughly a year and a half earlier, were pointed: toward in-package thermal management as a designed-in feature of stacked dies and redistribution layers, embedded within a continuous stream of fan-out, interposer, and stacked-transistor work. The record reads as a foundry treating heat removal as a packaging problem, on the same drawing board as the interconnect and the transistor.