Intel (INTC) led the week's semiconductor grants by volume, and the hardware among its issued patents is unusually coherent. Rather than ranging across unrelated ideas, the week-ending-May-1, 2026 grants converge on a single architectural problem and its consequence: stacking memory directly on top of logic to shorten the path between the two, and then handling the heat that vertical stacking traps. A granted claim is enforceable coverage, and the way a week's grants compose tells you what a company is staking position on. Intel's compose into one picture — vertical memory, integrated cooling, and the packaging that assembles the stack.

Stacking memory onto logic

Several grants describe putting memory arrays in layers above peripheral or logic devices. US12616012B2 covers stacked random-access memory with multilayer continuous vias that carry power and data between layers, with peripheral control devices placed in a separate layer from the memory arrays. US12615752B2 covers stacked SRAM with a shared wordline connection — vertically adjacent SRAM cells whose access transistors connect to a common wordline, which the grant frames as doubling word length for a given cell area. US12615762B2 covers a three-dimensional DRAM built from vertically aligned semiconductor structures, each with its own gate and capacitor and a shared vertical bit-line contact. The common thread is density and proximity: memory stacked over compute so data travels a shorter distance. The shared-wordline claim in US12615752B2 is a clear illustration — by connecting the access transistors of vertically adjacent SRAM cells to a common wordline, the design gets more storage out of a given footprint of silicon, which is the central economic lever in any memory-on-logic scheme. The 3D DRAM grant, US12615762B2, applies the same vertical logic to DRAM, stacking the semiconductor structures that form the cells and running a single bit-line contact down through them. Whether the memory is SRAM or DRAM, the filings describe trading horizontal area for vertical layers, which is the move that shortens the wire between memory and compute and, with it, the energy and latency of every access.

Cooling the stack from the inside

Stacking memory onto logic concentrates heat where it is hardest to remove, and the week's grants address that directly. US12616060B2 covers stacked SRAM with refrigeration — a cooling layer coupled to thermal interface layers by cold vias that carry a cold temperature into the stack. The grant states the mechanism plainly:

The cold vias transfer a cold temperature from the cooling layer to the thermal interface layer to cool the thermal interface layer and, in turn, the memory arrays.— Stacked random-access memory devices with refrigeration, US12616060B2

At the system level, US12615736B2 covers an immersion cooling system with a tank, an overflow chamber, and a perforated plate that directs coolant toward an outlet. The pairing matters: a company filing on cold-via cooling inside the die stack and on immersion cooling around the package is covering thermal management at two scales of the same problem. For a business reader, the operative point is that the cooling claims are not separate from the memory claims — they are the enabling condition for the stacked-memory architecture the other grants describe.

Holding the stack together: packaging and die-to-die

The third theme is the advanced packaging that assembles such systems from multiple dies. US12616042B2 covers a microelectronic assembly with a bridge die nested in a substrate cavity and an anchor layer around it, electrically coupled to a die above by conductive vias. US12616013B2 covers a dielectric-bondable chiplet for a package architecture with through-substrate vias, and US12616026B2 covers a microelectronics package built around a glass layer with embedded interconnects. The communication between dies is covered by US12615209B2, which describes inter-chiplet routing of transactions across heterogeneous chiplets using hierarchical addressing, where each message carries an identifier for both the destination chiplet and the destination agent on it. Owning the bridge, the chiplet bonding, the glass-layer interconnect, and the addressing scheme is coverage on how a multi-die product is physically and logically composed. The hierarchical-addressing detail in US12615209B2 is the logical counterpart to the physical packaging claims: a destination identifier split into a chiplet portion and an agent portion is the kind of routing scheme that lets a system scale to many heterogeneous chiplets without every die needing to know the full topology. That pairs naturally with the glass-layer and bridge-die packaging — the physical structure carries the signals, and the addressing scheme decides where they go. For a company building a foundry business around mixing dies from different processes into one package, holding coverage on both the physical assembly and the logical routing is coverage on the chiplet model itself.

Read together, the week's grants describe an end-to-end architecture: stack memory vertically onto logic (US12616012B2, US12615752B2, US12615762B2), cool the stack from inside and around it (US12616060B2, US12615736B2), and assemble and connect the dies through advanced packaging and die-to-die routing (US12616042B2, US12616013B2, US12616026B2, US12615209B2). The week also includes a gate-all-around device grant, US12615813B2, with vertically discrete source/drain structures — front-end transistor work consistent with the same vertical-integration theme. For a company positioning its foundry and product lines around advanced packaging, that is coverage on the full architecture, not a single layer of it.

The standard caution holds: a granted claim is coverage, not product, and it says nothing on its own about whether any of these structures ship or how widely they are used. What the week documents is direction. Intel's grants this week are concentrated on stacking memory onto logic, cooling the result, and packaging the dies that make it — a coordinated footprint around vertical integration rather than a set of unrelated devices. The patent record shows a company staking position on an entire stacked-memory-and-cooling architecture.