What Intel just locked in is more telling than what it announced. In the U.S. patents issued on 14 April 2026, Intel Corporation took a cluster of grants that share one idea: putting memory where logic is, by stacking memory arrays on top of — or bonded directly to — the transistor layers of a chip. Because these are issued grants rather than applications, each is enforceable coverage, and the set maps the device-level building blocks behind a strategy Intel has been telegraphing at the architecture level for years.

The anchor grant is US12604481B2, which claims integrated circuits with multiple levels of embedded memory — arrays of ferroelectric capacitors coupled to thin-film access transistors in a one-transistor/one-ferroelectric bit-cell, with the levels either monolithically built one over another or bonded face-to-face onto a host die. In plain business terms, that is memory fabricated into the same package as the processor instead of sitting in separate DRAM modules across a bus. Reinforcing it, US12604479B2 claims a two-transistor capacitorless memory cell built from stacked thin-film transistors — a write transistor over a read transistor, with no capacitor at all. The abstract states the structural choice directly:

Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor.— Two transistor capacitorless memory cell with stacked thin-film transistors, US12604479B2

From storage to in-array compute

The same grant week extends the footprint from storing data to computing on it. US12602200B2 claims an analog multiply-accumulate unit for multibit in-memory computing, in which a bank of capacitors performs the multiply-and-accumulate math that dominates neural-network inference, generating an analog result from digital signals read out of a memory array. That is the same memory-wall problem the broader industry is chasing — doing the arithmetic where the data already sits, rather than moving it to a separate accelerator — and a granted claim on an in-array MAC unit is enforceable coverage on one way to do it. The thread tying these together is that Intel is being granted claims across both halves of the memory-meets-logic problem: the memory cell itself and the compute that runs against it.

Two more grants in the set address the logic and packaging scaffolding such stacking requires. US12604531B2 claims a standard-cell architecture without dedicated power-delivery space allocation — a layout move closely associated with backside power delivery, where the power rails move beneath the transistors to free up routing on top. And US12604494B2 claims gate end-cap and work-function engineering to tune the threshold voltage of N-MOS transistors — the kind of granular device-tuning IP that underpins a manufacturable node. On the packaging side, US12604522B2 claims a universal electrically inactive "dummy" device for integrated-circuit packages, a mechanical-fill component used when heterogeneous dies are assembled into one package — the assembly problem you inherit the moment you start bonding memory and logic together.

It is worth being precise about why these particular memory types recur in the grants. Ferroelectric memory and capacitorless thin-film cells share a property that matters for the memory-on-logic idea: both can be built in the metal layers above the transistors, at lower temperatures than conventional DRAM capacitors, which is what makes it physically possible to stack them onto a finished logic die rather than fabricating them on a separate wafer. The grant on monolithically stacked ferroelectric levels (US12604481B2) and the grant on the 2T capacitorless cell (US12604479B2) are, in that sense, two routes to the same destination — embedded memory that lives on top of logic — and holding claims on both is the footprint of a company keeping more than one device option open. That breadth, rather than any single claim, is what makes the cluster read as a strategy rather than an experiment.

What the footprint establishes — and what it doesn't

Mapped together, the 14 April grants describe a coherent area of coverage: embedded memory cells (ferroelectric and capacitorless), the in-array compute to use them, the standard-cell and transistor-tuning IP to build the logic underneath, and the packaging components to assemble the result. For a company whose business case rests on differentiating its manufacturing and packaging — Intel Foundry's pitch to external customers leans on advanced packaging and the move to backside power — enforceable claims across this stack are the kind of footprint that puts freedom-to-operate pressure on anyone building memory-on-logic parts that touch the U.S. market.

The limits are the usual ones for a grant read. A patent grant confirms a claim cleared novelty and non-obviousness; it does not confirm volume production, yield, or a shipping product, which are the variables that decide whether embedded memory becomes a real revenue line. U.S. grants also lag the filing decisions behind them, so an April 2026 issue week reflects priorities set years earlier rather than a live roadmap. And a single company's claims do not exist in isolation: the same broader 14 April grant set shows memory and logic peers — Micron, Qualcomm, Samsung, and others — issued patents in adjacent device territory, which is what one expects when stacked memory-on-logic is an industry-wide direction rather than a solo bet. What the week establishes is that Intel converted a coordinated body of memory-on-logic filings into enforceable U.S. coverage in a single grant cycle — coverage that maps where it has chosen to plant claims as the boundary between memory and compute keeps eroding.