Qualcomm (QCOM) is filed in most people's minds as a modem and applications-processor company — the wireless IP and the Snapdragon system-on-chip. The grants issued to it in the week ending May 15, 2026 tell a quieter story. Alongside the expected stack of wireless patents, Qualcomm locked in enforceable coverage on the layers underneath the modem: the transistor itself, the way dies are stacked into a package, and the memory and power circuitry on the chip. For a fabless company that buys manufacturing from foundries, staking claims on how the silicon is physically built and assembled is a notable place to be spending its patent budget.

A granted claim is enforceable coverage, and the composition of a week's grants says more than the count. Qualcomm's hardware grants this week are not scattered — they line up along a single axis: vertical integration, from the transistor up through the package.

The transistor: a gate-all-around grant

The clearest marker is US12628377B2, a gate-all-around (GAA) field-effect transistor — the nanosheet device architecture that replaces the FinFET at the leading edge — built with different crystalline orientations for its p-type and n-type channels. The claimed point is carrier mobility: electrons and holes move best through silicon oriented differently, so using a different orientation for each transistor type balances their drive strength. The grant states the mechanism directly:

The different crystalline orientation channels improve the balance of carrier mobility for both carrier types (i.e., P-type and N-type) of GAA FETs in the GAA FET device.— Gate-all-around (GAA) field-effect transistor (FET) device having FETs with different crystalline orientation channels through a substrate, US12628377B2

For a business reader, the operative fact is the layer this claim sits at. Transistor architecture is the front-end-of-line work usually associated with foundries and IDMs. A fabless designer holding a granted GAA device claim has coverage on the device structure its own parts are built from — coverage it can carry into co-optimization with whichever foundry fabricates the design.

Stacking the system: SoC, power, and the package

The second theme is vertical integration of whole functional dies. US12628358B2 covers a device that stacks a system-on-chip die and a power-management IC (PMIC) die on opposite faces of a package substrate, with thin-film inductors on the PMIC delivering DC power directly to the SoC. Putting power delivery physically adjacent to the processor, on its own die, attacks the same droop-and-loss problem that backside power addresses at the wafer level — shortening the distance current travels to the compute that needs it.

US12628354B2 covers the package mechanics: a 3D IC package where a first die carries vertical interconnects that route signal and power between a second die and the package substrate. This is the chiplet-style assembly that lets a designer compose a product from multiple dies rather than one monolithic chip — and owning the vertical-interconnect scheme is coverage on how those dies talk to each other and to the board.

The third theme is the circuitry that feeds the compute. US12625614B2 covers charge-sensitive DRAM access-timing control — adjusting memory timing based on how much charge a row still holds, to cut latency on repeated accesses. US12626757B2 covers a low-latency multiplexed pipeline memory for a high-speed processor cache. And US12627229B2 covers a voltage booster with circuitry to reduce overvoltage stress on a discharge-protection device — power-management detail at the transistor level. Memory access timing, cache structure, and on-chip power are the unglamorous circuit-design work that decides how fast a processor can actually be fed and how reliably it runs. None of these will appear on a product spec sheet, yet they are precisely the layer a designer has to control to differentiate a system-on-chip when the underlying process node is one a competitor can also buy from the same foundry. Owning the cache and memory-timing IP is a way of competing on the parts of the design that are not commoditized by shared manufacturing.

Read together, the week's hardware grants form a coherent footprint from the transistor (GAA device) up through the chip's internals (cache, DRAM timing, power circuitry) to the assembled product (SoC-plus-PMIC stack, 3D interconnect package). For a company whose business has historically rested on wireless IP and processor design, that is coverage extending down and outward into device and integration territory — the layers that determine how a chiplet-era product is physically composed.

It is worth being precise about what "fabless" does and does not mean here. Qualcomm does not operate a fab, so a granted device-level claim is not a manufacturing capability — it is a position. But that position has commercial weight in the chiplet era, when products are co-designed with a foundry and the boundary between "design IP" and "process IP" blurs. A designer that holds claims on the transistor architecture, the die-stacking scheme, and the package interconnect carries negotiating and freedom-to-operate weight into those co-design relationships, and into any cross-licensing with the foundries and rivals working the same structures. The composition of the week's grants — front-end device through back-end assembly — is consistent with a company building that kind of stacked position deliberately rather than filing opportunistically wherever an engineer happened to innovate.

The standard caution holds: a granted claim is coverage, not product, and it says nothing on its own about whether a given structure ships or how widely it gets used. What the week documents is direction. Qualcomm's hardware grants this week are concentrated on building and assembling silicon — the transistor, the stack, the interconnect, the on-chip memory and power — rather than solely on the wireless and compute functions it is known for. The patent record shows a designer staking position on the inside of the chip, not just the radio.