International Business Machines (IBM) led every other assignee in US semiconductor grants for the week ending May 22, 2026 — issuing more than 50 chip-related patents, ahead of Samsung Electronics and Micron Technology (MU) on raw count. For a company that does not run a leading-edge logic foundry, the interesting question is not how many patents IBM was granted but where it locked in coverage. Read as a set, the week's grants land overwhelmingly on the parts of a chip that determine how far a process node can scale — backside power, transistor stacking, and new memory cells — rather than on the headline logic speed that dominates foundry marketing.

That distinction matters because IBM monetizes IP differently from TSMC or Intel. IBM is a research house and a licensor: its semiconductor work feeds joint-development programs, patent cross-licenses, and the technology that partners carry into volume production. A granted claim is enforceable coverage, and IBM's footprint this week reads as coverage staked across the enabling layers that every advanced-node maker has to traverse.

Backside power: the cluster's center of gravity

The single densest theme is backside power delivery — moving a chip's power-supply wiring from the crowded front of the wafer to the back, which frees routing space and cuts the voltage droop that throttles dense logic. IBM was granted US12635498B2, covering stacked devices with backside contacts; US12635505B2, on a power delivery network using "super vias" that connect non-adjacent metal layers; and US12635491B2, a replacement buried power rail. Together they describe the plumbing of backside power — the contacts, the rails, and the vias that route current up into the device.

The buried-power-rail grant is the clearest statement of where the value sits. Its claim is specific about the geometry that makes the structure work:

A critical dimension of the BPR may be larger than a distance between the first S/D and the second S/D.— Replacement buried power rail, US12635491B2

Backside power is one of the two or three features that define the sub-2nm node transition across the industry. Claims on the buried rail, the super-via network, and the backside contact scheme are coverage on the connective tissue that any maker adopting backside power has to build. For a licensor, that is the kind of position that sits underneath other companies' roadmaps rather than competing head-on with them.

Transistors and the device-architecture layer

The second theme is the transistor itself. US12635241B2 covers a fork-sheet field-effect transistor with airgap isolation — a structure that places a dielectric wall between adjacent nanosheet devices to pack them closer, a step beyond standard gate-all-around. US12635236B2 covers a stacked-FET architecture with separate gate regions, the complementary-FET idea of building one transistor directly above another to gain density without shrinking features further. These are the post-FinFET device structures the whole field is converging on, and IBM's grants put markers on the isolation and gate schemes that make them manufacturable.

The same week's research-paper trail backs the direction up: several of the transistor grants share inventors (Ruilong Xie appears across the backside-power and fork-sheet filings), which is consistent with a coordinated program rather than scattered one-off ideas. The footprint reads as device-architecture coverage built deliberately around the scaling roadmap, not a grab bag.

The same week's filings also extend the device work toward power and signal handling: IBM was granted US12635513B2, an interconnect structure that turns normally-unused space between power and ground lines into added decoupling capacitance, and US12635066B2, a thermally decoupled signal transmission line. Decoupling capacitance and thermal isolation are the quiet reliability problems that grow as power density climbs — and patenting them alongside the buried rail and the backside contacts rounds out a coverage map of the entire power-and-signal-delivery layer, not just one piece of it.

The footprint then moves off logic entirely and into new memory cells. US12635426B2 covers a resistive random-access memory (RRAM) device with a step-height difference; US12635425B2 covers a stacked conductive-bridge random-access memory; and US12635419B2 covers a stacked spin-orbit-torque magnetoresistive memory (MRAM). RRAM, CBRAM, and SOT-MRAM are the leading candidates to embed dense non-volatile memory directly on logic — the kind of on-chip memory that matters as AI workloads push data movement, not arithmetic, to the front of the cost equation. IBM staking coverage across all three cell types is breadth across the emerging-memory field rather than a bet on one winner.

For a business reader, the through-line is what kind of company files this way. A maker racing a competitor to a specific node would concentrate its grants on that node's logic. A research-and-licensing operation spreads coverage across the enabling layers — power delivery, device architecture, memory cells — that every maker has to license or design around. IBM's week is the second pattern. The grants put enforceable markers under the parts of the chip where the next several node transitions are actually constrained.

The usual caveat applies and cuts the way it always does: a granted claim is coverage, not revenue, and it says nothing on its own about how widely the structure gets adopted or licensed. What the week establishes is position. IBM did not lead the grant count by filing broadly across the chip; it led it by filing deep into backside power, transistor stacking, and emerging memory — the layers a licensor wants to own when the rest of the industry has to pass through them. By comparison, the same week's grants from Samsung and Micron skewed toward packaging and memory products they themselves ship, which is the difference between a manufacturer protecting its own line and a research house staking the enabling steps underneath everyone's.