The interesting number is the cadence. On 28 July 2026, 55 patents issued carrying an International Business Machines assignee, and a substantial share of them are about the same face of the wafer. US12696746B2 is the representative one — and it issued exactly seven days after US12690445B2, on inverted backside signal wiring, which this desk covered at the time.

Two grants a week apart on adjacent subject matter is not a coincidence to be noted and dropped. It is the shape of a programme reaching the end of its prosecution pipeline together.

A semiconductor device comprising: backside power rails located between at least one N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor spaces; and backside local signal lines located between the backside power rails, wherein the backside local signal lines connect to at least one source/drain or at least one gate through at least one backside contact.— Backside BPR/BSPDN integration with backside local interconnect, US12696746B2

What the claim adds to backside power

Backside power delivery is already a known direction: move the power rails from the crowded frontside wiring stack to the reverse of the wafer, freeing frontside tracks for signals and shortening the path from the rail to the transistor. What claim 1 of this grant adds is that the backside is not reserved for power. Between the backside power rails sit backside local signal lines, and those lines connect to a source/drain or a gate through a backside contact.

Claim 3 states the resulting geometry directly: a cell architecture with the backside local signal lines running horizontally on a backside, and a frontside metal running vertically. Signal routing is being split across both faces of the die, with each face taking one direction. That is a more aggressive proposition than backside power alone, because it makes the backside a wiring level with its own contacts rather than a power plane.

Claims 4 through 8 build the cell out transistor by transistor — a pair of adjacent N channel transistors with a backside N channel power rail between them, two adjacent P channel transistors with their own backside P channel rail, and the backside local signal lines running between the N and P devices. Claim 9 is a second independent claim reciting that arrangement directly rather than by dependency.

The rest of the 28 July set

The same issue day carries the supporting apparatus. US12696745B2 claims a composite contact running from a frontside contact along the side of a source/drain region down to a backside power element — the vertical connection this architecture requires. US12696739B2 covers a handler wafer with a 111 crystallographic direction silicon substrate for low overlay residual backside patterning, which is a manufacturing prerequisite: you cannot pattern the backside accurately unless the carrier holding the wafer does not distort it. US12696459B2 goes further and puts MRAM on the back side of the front-end layer while the devices stay on the front.

Alongside those sit stacking grants — US12696533B2 on split gate contacts for vertically stacked transistors and US12696484B2 on a back-end-of-line vertical-transport transistor built above the front-end circuitry — plus device-level work including air gaps flanking a source-drain contact via and paired nanosheet transistors with different inter-channel spacings and gate oxide thicknesses.

Read as a set, the theme is that the die is being treated as a volume with two usable surfaces and stackable device levels, rather than a plane with wiring piled on top. Power moves to the back, signals follow it, memory follows the signals, and transistors start appearing above the front-end layer. Each of those moves creates work for the others: backside signal lines need backside contacts, backside contacts need a carrier that holds the wafer flat enough to pattern against, and stacked devices need gate contacts that can be reached without shorting the level below. A portfolio that lands all of those in one issue day is one where the pieces were prosecuted as a system.

A grant establishes an enforceable position on the claimed subject matter as of issue. It does not establish a product, a node, a schedule or a manufacturing commitment, and nothing in this record names one. Filing and grant cadence is a directional indicator of where sustained engineering money has gone — the applications underlying a July 2026 issue were filed years earlier — but it is not a disclosure of capex, and no spending figure should be inferred from a patent count. What it does support is a statement about direction: the engineering that produced these claims was funded, sustained and prosecuted to completion, and it was pointed at the same face of the wafer for long enough to arrive in two consecutive issue weeks.

One caution on the count itself. Fifty-five is the number of records in this issue day carrying an IBM assignee in the index searched; assignee fields are inconsistently populated across any given day, so treat it as a floor rather than a total. The assignee also appears in two casings, "International Business Machines Corporation" and "INTERNATIONAL BUSINESS MACHINES CORPORATION", which must be summed rather than read from a single facet.

Two published-text details, reproduced rather than repaired: claim 1 reads "between at least one N channel field effect transistor to N channel field effect transistor spaces", pairing a singular qualifier with a plural noun, and the abstract uses "space" singular for the P channel case where claim 1 uses "spaces". Claim 9 opens an element with "a N channel transistor" rather than "an".