A memory company's published patent applications are one of the cleaner windows into what it thinks the next several years look like, because an application is an idea a company paid to file roughly 18 months before it surfaces. So when a batch of Micron Technology (MU) applications published on 23 April 2026 reads less like "how to store more bits" and more like "how to do math where the bits already live," that shift is the signal worth reading. Micron is the only U.S.-based memory pure-play among the DRAM and NAND leaders, and the direction of these filings says something about where it is steering R&D as AI reshapes what customers want from memory.

The clearest cluster is in-memory compute. Two of the published applications, US20260113009A1 and US20260112422A1, describe doing the analog math of a neural network directly inside a flash memory by sensing current off memory cells and feeding it into a transimpedance amplifier — an amplifier that turns a current into a voltage. The second application frames the move plainly:

The controller might further be configured to cause the memory to convert the output voltage level to a digital value representative of the sampled current level.— Analog Processing of Activation Functions, US20260112422A1

The business idea underneath the circuitry is straightforward. The expensive, power-hungry part of running an AI model is shuttling data between the processor and the memory — the so-called memory wall. If some of the multiply-and-accumulate work that a neural network does can happen inside the memory array itself, using the physics of the cells, the data does not have to move as far. A memory vendor that owns IP on doing that work in-array is filing toward a future where the line between "memory" and "compute" blurs — and where memory carries more of the value of an AI system rather than being the commodity layer underneath someone else's accelerator.

Quantifying the cluster helps keep it honest. Of the six Micron applications that published on 23 April 2026, two are explicitly framed around analog processing of neural-network activation functions, one around a 2D-material transistor structure, one around a contact-efficient read-only-memory array, and two around array control and read-error reliability. That is a small batch in absolute terms, but it is tightly themed: every one of the six touches either how computation is done inside or adjacent to the array, or how a denser array is made to work reliably. A scattershot filing week would spread across unrelated subsystems; this one does not. For a reader tracking where a memory vendor is spending, the concentration is the point — the applications read as pieces of one program rather than six independent ideas.

Beyond storage: exotic channels and read-only arrays

The same publication set shows Micron filing on the device physics that would underpin denser, lower-power memory-compute. US20260113977A1 describes an integrated assembly in which a two-dimensional material — the family that includes graphene-like atomically thin semiconductors — runs along the sidewall of an upwardly-extending structure, with electrostatic-doping regions and a gate forming a transistor. 2D-channel devices are a long-horizon bet on transistors that can be stacked vertically and run at very low leakage, exactly the properties you want for memory-adjacent logic. Separately, US20260113933A1 describes a read-only-memory array engineered so the number of contacts is smaller than the full word-line-times-data-line grid — a cost-and-density play for the kind of fixed-weight storage an embedded AI model might use.

Rounding out the cluster are filings on the supporting machinery of a memory device: US20260112401A1 describes a memory-array architecture using a column repeater to drive selection signals across a large array, and US20260112436A1 describes triggering additional word-line scans to catch read errors before a block goes bad — reliability engineering for denser arrays. Neither is glamorous on its own, but they are the kind of array-level plumbing a company files when it is trying to make a larger, denser, more aggressively used array behave predictably. Bundled with the analog-compute and device filings, they fill out the picture of a memory maker working the full vertical of the problem — the cells, the math run against them, and the control logic that keeps a scaled array usable — rather than chasing a single feature in isolation. Taken together, the set spans the analog compute layer, the device layer, and the array-control layer, which is the footprint of a company working a problem end to end rather than dabbling.

The caveats are the standard ones for applications, and they matter. These are publications, not grants; the claims can be narrowed or rejected before any patent issues, and a filed concept is not a shipping product line. The 18-month publication lag also means this reflects spending decisions Micron made well before the publication date, not a live readout of its current roadmap. In-memory analog compute in particular has been an industry research theme for years without yet displacing conventional accelerators at scale, so the presence of the IP does not establish commercial traction. What the cluster does establish is direction: a memory maker funding the work to put computation, exotic-channel transistors, and AI-shaped storage inside the array — the part of the stack a DRAM and NAND vendor would build out if it intended memory to be more than the commodity layer in the AI buildout. The contemporaneous activity confirms the lane is contested; in the same week's broader semiconductor publications, memory and logic peers were filing on adjacent device and array structures, which is what one expects when several large players are reading the same trend at once.