The capex-meets-IP fact first: at advanced nodes, performance is increasingly limited not by the transistor channel but by the resistance where wires meet the device. US11756996B2, granted September 2023 to IBM, patents forming a wrap-around contact for gate-all-around nanosheet transistors (CPC H01L 29/0673).

Gloss it once. A contact is where the metal wiring connects to the transistor’s source and drain. As devices shrink, the contact area shrinks too, and the resistance there climbs — throttling current and slowing the transistor. A “wrap-around” contact increases the contact area by surrounding the source/drain region, lowering resistance and recovering performance.

“Each source/drain region includes bridging structures respectively connected to each nanosheet channel layer.”— U.S. Patent No. 11,756,996 source

The clever part is the geometry the patent uses to manufacture that wrap-around contact in a stacked device. In a gate-all-around nanosheet transistor, the channels are stacked, and the source/drain has to connect to each one. The patent describes “bridging structures” — separate epitaxial stubs, one per nanosheet channel layer — that connect each channel out to the source/drain region. Claim 1 then specifies a metal wrap-around-contact that sits in the spaces between those bridging structures and “encapsulat[es]” them, so the bridging structures are entirely embedded in metal and each is separated from the others. Instead of metal touching only the outer face of a merged source/drain, the contact metal reaches in among the per-channel stubs and wraps each one — multiplying the metal-to-semiconductor interface area, which is what lowers resistance.

The dependent claims show how much process detail this requires, and that detail is the moat. The substrate is silicon with a specific (110) crystal orientation while the source/drain epitaxy is a single merged Si (100) component (claims 1, 2, 4). The bridging structures are doped for polarity — boron-doped SiGe for a PFET, phosphorus-doped silicon for an NFET (claims 5–6). Claim 9 even pins a dimension: a source/drain region width of 10–20 nanometers. And claim 8 extends the scheme to a shared source/drain between adjacent transistors, with each bridging structure tying into both devices’ channels. This is not a concept sketch; it is a recipe for forming low-resistance contacts to every layer of a stacked nanosheet device at single-digit-to-low-double-digit nanometer dimensions.

Why a capex desk reads it: the benefit of an expensive new node can be eaten away by parasitic resistance if contacts are not addressed. Contact engineering is part of what makes a node deliver its promised performance, which is part of what justifies its capex. A patent that specifies bridging structures, full metal encapsulation, crystal orientations, and dopant chemistries is exactly the enabling IP that turns nanosheet’s theoretical speed into delivered speed — and IBM’s research arm often pioneers these techniques ahead of the foundries that license or independently develop them.

The period framing matters. In 2023, gate-all-around nanosheet transistors were entering production, and the supporting contact and interconnect techniques had to keep pace. A device with stacked channels is useless if you cannot wire each channel out at low resistance; an IBM wrap-around-contact grant addressing exactly that reflects the build-out of the resistance-fighting toolkit the new transistor needs.

The shared-source/drain claim deserves a closer read because it shows the patent thinking at the layout level, not just the single-device level. Claim 8 covers a pair of adjacent transistors that share one source/drain region, with each bridging structure in that shared region connecting to the corresponding nanosheet layers of both devices while the wrap-around metal stays set apart from the stubs. Sharing a source/drain between neighbors is a standard density move; doing it while still wrapping metal around per-channel bridging structures for low resistance is the hard part, because the geometry gets cramped exactly where you most need clean metal fill. That the patent claims the combination — density via sharing and performance via wrap-around contact in the same structure — is what makes it valuable as an enabling technique rather than a point solution.

The financial logic is that contact resistance is a tax on every transistor, and at nanosheet dimensions it can quietly consume a large fraction of the performance the node was supposed to deliver. A foundry or IDM that has solved low-resistance contacts to stacked channels gets more of the speed it paid for when it built the process, and a research house like IBM that invents and patents the technique can license it broadly or trade it in cross-licensing. Either way the grant is a claim on a piece of the performance budget of an entire generation of logic — the kind of upstream IP whose value shows up indirectly, in how well everyone’s nanosheet chips actually run.

The caveat we attach: this is a process patent and a defensive/licensing asset. It evidences where the contact technique was invented and the specific bridging-structure and encapsulation scheme claimed; it does not quantify the resistance reduction or establish who ships it.

The patent also goes out of its way to keep the bridging structures unmerged, and that emphasis is technically revealing. Across claims 3, 5, 9, and 10 the bridging structures “do not contact each other” and are “void of being merged together,” even as the source/drain epitaxy itself can be a single merged Si (100) component. Keeping the per-channel stubs separated is what lets the wrap-around metal flow into the gaps between them and encapsulate each one; if they merged, the metal would only touch the outside and the resistance advantage would collapse. The claims pin the polarity chemistry to match — SiGe:B stubs for PFETs, Si:P stubs for NFETs — and add a metal contact landing on the wrap-around metal to form the conductive path to all the channel layers (claim 10). It is a coherent recipe in which every constraint exists to maximize the metal-to-semiconductor interface.

For the period investor, the lesson is that node performance is a fight against parasitics, and contacts are a major front. A 2023 wrap-around-contact grant — reaching metal in among per-channel bridging stubs to wrap each one — is one move in that quiet, decisive battle.