The capex-meets-IP fact first: at advanced nodes, performance is increasingly limited not by the transistor channel but by the resistance where wires meet the device. US11756996B2, granted September 2023 to IBM, patents forming a wrap-around contact for gate-all-around nanosheet transistors (CPC H01L 29/0673).
Gloss it once. A contact is where the metal wiring connects to the transistor's source and drain. As devices shrink, the contact area shrinks too, and the resistance there climbs — throttling current and slowing the transistor. A "wrap-around" contact increases the contact area by surrounding the source/drain region, lowering resistance and recovering performance.
Why a capex desk reads it: the benefit of an expensive new node can be eaten away by parasitic resistance if contacts are not addressed. Contact-engineering IP is part of what makes a node deliver its promised performance, which is part of what justifies its capex. IBM's research IP often pioneers exactly these techniques.
The period framing matters. In 2023, gate-all-around nanosheet transistors were entering production, and the supporting contact and interconnect techniques had to keep pace. An IBM wrap-around-contact grant reflects the build-out of the resistance-fighting toolkit the new transistor needs.
The caveat we attach: this is a process patent and a defensive/licensing asset. It evidences where the contact technique was invented; it does not quantify the resistance reduction or establish who ships it.
For the period investor, the lesson is that node performance is a fight against parasitics, and contacts are a major front. A 2023 wrap-around-contact grant is one move in that quiet, decisive battle.